URL https://opencores.org/ocsvn/eco32/eco32/trunk

Subversion Repositories eco32

[/] - Rev 80

Rev	Log message	Author	Age	Path
80	hwtests/xcptest now tests the bad address register too	hellwig	3784d 15h	/
79	hwtests (kbd): second timer added	hellwig	3785d 05h	/
78	simulator: tlbBadAddr register is now called mmuBadAddr	hellwig	3786d 08h	/
77	hardware: ucf file re-formatted	hellwig	3787d 11h	/
76	AUTHORS update	hellwig	3788d 03h	/
75	hardware: cpu now equal to port-15	hellwig	3788d 03h	/
74	when simulating the system include a console	hellwig	3788d 08h	/
73	use xess monitor when simulating the system	hellwig	3788d 08h	/
72	simulator: IRQ 0-3 explanation changed	hellwig	3788d 11h	/
71	simulator: IRQ 15 explanation added	hellwig	3788d 11h	/
70	hardware: two timers	hellwig	3789d 04h	/
69	hardware: timer counts clock cycles, counter is readable	hellwig	3789d 06h	/
68	hardware: timer now equal to port-15	hellwig	3789d 10h	/
67	fpga implementation update	hellwig	3789d 13h	/
66	bin2exo: no S0 header any longer	hellwig	3790d 06h	/
65	xess monitor update	hellwig	3790d 08h	/
64	monitors re-organized	hellwig	3790d 11h	/
63	monitors re-organized	hellwig	3790d 11h	/
62	monitors re-organized	hellwig	3790d 12h	/
61	monitors re-organized	hellwig	3790d 12h	/
60	monitors re-organized	hellwig	3790d 12h	/
59	monitors re-organized	hellwig	3790d 12h	/
58	monitors re-organized	hellwig	3790d 12h	/
57	monitors re-organized	hellwig	3790d 12h	/
56	monitors re-organized	hellwig	3790d 13h	/
55	xess monitor update	hellwig	3790d 13h	/
54	digilent monitor update	hellwig	3790d 14h	/
53	monitor update	hellwig	3791d 02h	/
52	serial.h in monitor added	hellwig	3791d 06h	/
51	both monitors	hellwig	3791d 06h	/