OpenCores
URL https://opencores.org/ocsvn/eco32/eco32/trunk

Subversion Repositories eco32

[/] - Rev 96

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
96 standalone program memsize executable at 0xC0010000 hellwig 3763d 05h /
95 standalone program hello2 executable at 0xC0010000 hellwig 3763d 05h /
94 standalone program hello executable at 0xC0010000 hellwig 3763d 05h /
93 compiler: -Wo-kernel relocates code to 0xC0010000 hellwig 3764d 05h /
92 compiler: -Wo-kernel relocates code to 0xC0010000 hellwig 3764d 05h /
91 simulator: -a sets load address for -l in command line hellwig 3764d 07h /
90 EOS32 boot update hellwig 3764d 21h /
89 EOS32 boot update hellwig 3765d 05h /
88 monitor: do not set sp on bootstrap hellwig 3765d 06h /
87 disk: master boot made compatible with monitor hellwig 3766d 01h /
86 disk: master boot made compatible with monitor hellwig 3766d 16h /
85 monitor: bootstrap parameters modified hellwig 3767d 00h /
84 monitor: bad address register added hellwig 3767d 07h /
83 simulator: individual help messages hellwig 3767d 20h /
82 simulator: change command @ -> #, better help for commands hellwig 3767d 21h /
81 hardware: cpu now has a bad address register hellwig 3768d 06h /
80 hwtests/xcptest now tests the bad address register too hellwig 3768d 07h /
79 hwtests (kbd): second timer added hellwig 3768d 22h /
78 simulator: tlbBadAddr register is now called mmuBadAddr hellwig 3770d 01h /
77 hardware: ucf file re-formatted hellwig 3771d 04h /
76 AUTHORS update hellwig 3771d 19h /
75 hardware: cpu now equal to port-15 hellwig 3771d 20h /
74 when simulating the system include a console hellwig 3772d 00h /
73 use xess monitor when simulating the system hellwig 3772d 01h /
72 simulator: IRQ 0-3 explanation changed hellwig 3772d 04h /
71 simulator: IRQ 15 explanation added hellwig 3772d 04h /
70 hardware: two timers hellwig 3772d 20h /
69 hardware: timer counts clock cycles, counter is readable hellwig 3772d 23h /
68 hardware: timer now equal to port-15 hellwig 3773d 03h /
67 fpga implementation update hellwig 3773d 05h /

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.