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Rev Log message Author Age Path
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 4705d 06h /
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4705d 08h /
355 Import Julius Baxter's verilator hints from ORPSoC olof 4705d 09h /
354 Whitespace cleanup olof 4705d 09h /
353 Inherit fixes for bit width of constants from ORPSoC olof 4707d 11h /
352 Removed delayed assignments from rtl code olof 4711d 17h /
351 Turn defines into parameters in eth_cop olof 4720d 07h /
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4720d 07h /
349 Make all parameters configurable from top level olof 4721d 08h /
348 Added option to dump VCD files olof 4722d 07h /
347 Added information about running with Icarus Verilog olof 4722d 07h /
346 Updated project location olof 4722d 09h /
345 Temporarily disable failing tests olof 4722d 11h /
344 bit 9 in phy control register is self clearing olof 4728d 13h /
343 Address miss should not be asserted on short frames olof 4732d 09h /
342 Added cast to avoid inequality when comparing different data types olof 4732d 09h /
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4732d 09h /
340 Don't fail if log dir already exists olof 4733d 07h /
339 Added basic support for Icarus Verilog olof 4734d 06h /
338 root 5526d 12h /
337 root 5582d 14h /
336 Added old uploaded documents to new repository. root 5583d 17h /
335 New directory structure. root 5583d 17h /
334 Minor fixes for Icarus simulator. igorm 7031d 19h /
333 Some small fixes + some troubles fixed. igorm 7032d 07h /
332 Case statement improved for synthesys. igorm 7045d 12h /
331 Tests for delayed CRC and defer indication added. igorm 7060d 14h /
330 Warning fixes. igorm 7060d 14h /
329 Defer indication fixed. igorm 7060d 16h /
328 Delayed CRC fixed. igorm 7060d 16h /

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