URL https://opencores.org/ocsvn/ethmac10g/ethmac10g/trunk

Subversion Repositories ethmac10g

[/] - Rev 29

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Rev	Log message	Author	Age	Path
29	no message	fisher5090	6733d 17h	/
28	First commit. 32-bit counter. Synthesizes with no errors in Xilinx XST.	mvpratt	6736d 04h	/
27	xilinx coregen	fisher5090	6746d 08h	/
26	good edition	fisher5090	6746d 09h	/
25	no message	fisher5090	6746d 09h	/
24	First cut. One of the main culprits for the timing violations.	godzilla	6749d 00h	/
23	First cut. Original code from Easic but add some extra controls. One of the main culprits for the timing violations.	godzilla	6749d 00h	/
22	First cut. Original code from Easic but add some extra controls.	godzilla	6749d 00h	/
21	First cut. Not thoroughly tested yet but still need to implement the configuration, non-crc version and stats. So far Leonardo Precison indicates the design can run upto 101 MHz but need to remove the timing violations to increase speed.	godzilla	6749d 00h	/
20	First cut. Still need to update the document with design changes.	godzilla	6749d 00h	/
19	First cut.	godzilla	6749d 00h	/
18	works well	fisher5090	6753d 13h	/
17	crc test	fisher5090	6753d 20h	/
16	use counter	fisher5090	6757d 05h	/
15	crc module	fisher5090	6757d 05h	/
14	no more used	fisher5090	6757d 05h	/
13	first commit. not yet ready to compile	mvpratt	6757d 05h	/
12	200MHZ	fisher5090	6758d 14h	/
11	200MHZ	fisher5090	6758d 14h	/
10	200MHZ	fisher5090	6758d 14h	/
9	with max frequence of 200MHZ	fisher5090	6764d 09h	/
8	achieve 111M	fisher5090	6766d 11h	/
7	passed post-map simulate	fisher5090	6767d 18h	/
6	removed files	fisher5090	6770d 06h	/
5	receive engine initial codes	fisher5090	6770d 06h	/
4	no message	fisher5090	6770d 10h	/
3	test for CVS	fisher5090	6827d 08h	/
2	test for CVS	fisher5090	6829d 21h	/
1	Standard project directories initialized by cvs2svn.		6829d 21h	/

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Subversion Repositories ethmac10g

[/] - Rev 29

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