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Rev Log message Author Age Path
35 Added support for stacked MPLS UDP/IPv4/IPv6 PTP packets. edn_walter 4495d 23h /
34 Added LGPL file header to all copyrighted files. edn_walter 4496d 02h /
33 Redefined memory map. RTC and TSU now have separate address spans, can be easily divided into to independent modules. edn_walter 4496d 03h /
32 Added PTP standard time format output to the top module. Can be connected to external modules. edn_walter 4496d 05h /
31 Added hand-shaking for the TSU data reading. edn_walter 4496d 23h /
30 Timestamp format in the queue = msgId_4bit + seqId_16bit + null_8bit + timeStamp1s_4bit + null_2bit + timeStamp1ns_30bit edn_walter 4496d 23h /
29 Added multicycle timing constraint to ptp_parser.v, which works at data rate of (32bit * 4 gmii_clk cycle). Fmax can exceed 250MHz. edn_walter 4496d 23h /
28 Before changing TSU packet parser datapath width from 32b to 8b. edn_walter 4497d 05h /
27 Added more bits to the TSU queue information, of which timestamp value is enlarged from 4s to 64s. edn_walter 4497d 05h /
26 Updated test case. edn_walter 4499d 00h /
25 Updated SOPC Builder component and example system. edn_walter 4499d 23h /
24 Added test cases for top-level testbench to cover both RTC and TSU. edn_walter 4500d 01h /
23 Added CDC hand-shaking for RTC time reading operation. edn_walter 4500d 19h /
22 RTC reset will clear ACC counter, but not clear ACC counter incremental. edn_walter 4500d 23h /
21 Added structure for top-level simulation. Systemverilog DPI will be used to emulate the SW operation of PTP application. edn_walter 4501d 19h /
20 Added SOPC Builder Component and Instantiation Example. Follow rtl/sopc/ReadMe.txt to add IP Search Path to SOPC Builder. edn_walter 4505d 23h /
19 Added pipeline registers to Real Time Clock module to improve timing. edn_walter 4505d 23h /
18 Added QuartusII Place and Route project for top level ha1588.v edn_walter 4506d 00h /
17 Updated reg.v content. edn_walter 4506d 17h /
16 Try to add sth. edn_walter 4510d 10h /
15 Renamed module name for tsu and rtc.
Added folder for reg and top.
Added folder for sopc, preparing for Altera SOPC Builder customized component.		 edn_walter 4512d 19h /
14 Added test case support for UDP/IPv6 PTP frames. edn_walter 4514d 19h /
13 Added test case support for single VLAN and double VLAN L2/L4 PTP frames. edn_walter 4515d 19h /
12 Added parser support for vlan tagged frames. edn_walter 4516d 17h /
11 Added parser support for L2_PTP and IPv4/v6_UDP_PTP frame formats. edn_walter 4517d 19h /
10 Added parser support for L2_PTP and IPv4_UDP_PTP frame formats. edn_walter 4518d 19h /
9 Timestamp format in the queue = seqId_16bit + msgId_4bit + timeStamp1s_2bit + timeStamp1ns_30bit edn_walter 4519d 18h /
8 Timestamp format in the queue = seqId_16bit + msgId_2bit + timeStamp_30bit edn_walter 4520d 01h /
7 Reduced the timestamp length from 80b to 30b to save memory, since the software could be fast enough to handle timestamp rollover events per 1s. Enlarged the fifo depth to 15, to accomodate 10 ptp sync messages per 1s. edn_walter 4520d 02h /
6 Reduced the size of the Vendor specific simulation library file. ash_riple 4522d 01h /

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