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Rev Log message Author Age Path
101 FIX: code_rd_vma asserted only after reset is done
ADDED cache control bits to CP0 status register
ADDED cache control outputs		 ja_rd 4845d 10h /
100 Obsolete synthesizable template files removed ja_rd 4869d 19h /
99 Obsolete TB template files removed ja_rd 4869d 19h /
98 CPU rd and wr data address buses unified ja_rd 4869d 19h /
97 CPU rd and wr data address buses unified ja_rd 4869d 19h /
96 CPU rd and wr data address buses unified ja_rd 4869d 19h /
95 BUG FIX: cache stub properly handles all kind of cycles now ja_rd 4880d 15h /
94 Pregenerated demo 'hello' files updated ja_rd 4880d 15h /
93 SW simulator supports 'log trigger address' and keyboard input as simulated UART RX.
Project parameters now launch adventure demo automatically		 ja_rd 4880d 15h /
92 'hello' demo updated to use new startup files ja_rd 4880d 15h /
91 FIX: startup files can now be used to run from FLASH or BRAM ja_rd 4880d 15h /
90 Added 'Adventure' demo to be run from the DE-1 FLASH ja_rd 4880d 15h /
89 Added startup and utility functions for 'bare metal' applications running from FLASH, plus linker file ja_rd 4880d 15h /
88 Added UART RX interface to MPU template ja_rd 4880d 15h /
87 Added UART RX interface to MPU template ja_rd 4880d 15h /
86 Adapted TB template to use log trigger address ja_rd 4880d 15h /
85 BUG FIX: log2 function was wrong ja_rd 4880d 15h /
84 Added 'trigger address' for file logging to both the
vhdl TB and the python script		 ja_rd 4880d 15h /
83 BUG FIX: LHU was not doing sign extension properly
BUG FIX: SLTIU decoding was wrong		 ja_rd 4880d 16h /
82 bug fix: SLTI wasn't working properly in some cases ja_rd 4882d 16h /
81 Added a wait state to the SRAM area for the DE-1 demo code ja_rd 4889d 10h /
80 Stub cache fixed
Now supports code refills from static 16- and 8- bit memory
Plus many mirror corrections		 ja_rd 4889d 10h /
79 modelsim wave window script updated ja_rd 4890d 12h /
78 Code sample 'memtest' adapted to test read from flash ja_rd 4890d 13h /
77 Simulation template now supports simulated flash
Synthesis template adapted to latest cache interface
Python script now supports simulated flash		 ja_rd 4890d 13h /
76 Adapted pregenerated vhdl files to latest changes ja_rd 4890d 13h /
75 Added support for 8-bit-wide static memory (e.g. Flash)
Updated demo 'top' file to use the DE-1 onboard flash		 ja_rd 4890d 13h /
74 Fixed (harmless) error in simulation template 2 ja_rd 4890d 17h /
73 Fixed comment about write cycles in cache module ja_rd 4890d 17h /
72 Fixed stupid bug in SRAM write cycles (setup time violated)
Wait states implemented for SRAM wait and read cycles		 ja_rd 4890d 17h /

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