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[/] - Rev 155

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Rev	Log message	Author	Age	Path
155	Temporary warning added to outdated project doc file	ja_rd	4786d 16h	/
154	fixed log trigger address in hello makefile	ja_rd	4786d 17h	/
153	Added R3000 compatible support for kernel/user state: - Implemented KU/IE plus KUp/IEp and KUo/IEo status bits - Updated startup and test code to account for changes - Implemented bit DID NOT TEST rfe instruction (not used in code) - Access to CP0 in user mode triggers 'CpU' trap - Updated software simulator Besides, the logging of HI/LO register changes has been temporarily disabled, there's an unfixed bug in it.	ja_rd	4786d 17h	/
152	Added R3000 compatible support for kernel/user state: - Implemented KU/IE plus KUp/IEp and KUo/IEo status bits - Updated startup and test code to account for changes - Implemented bit DID NOT TEST rfe instruction (not used in code) - Access to CP0 in user mode triggers 'CpU' trap - Updated software simulator Besides, the logging of HI/LO register changes has been temporarily disabled, there's an unfixed bug in it.	ja_rd	4786d 17h	/
151	BUG FIX: major bugs fixed in cache module 1.- sram address was wrong (leftover from previous version) 2.- writes to unmapped areas were blocking the cache 3.- Sequence SW,LW produced a RAW data hazard in some cases	ja_rd	4786d 17h	/
150	Bug fix: added missing nop in vacant branch delay slot	ja_rd	4787d 14h	/
149	changed size of simulated flash in opcodes sample code	ja_rd	4787d 14h	/
148	Added optional cache support to 'opcodes' test. Updated simulation length accordingly.	ja_rd	4789d 06h	/
147	SW simulator updated to latest HW revision (plus a few mistakes corrected: wrongly commented out lines, mostly)	ja_rd	4789d 06h	/
146	Added D-Cache setup code to 'adventure' bootstrap code (redundant since common C startup code already does it but...)	ja_rd	4789d 07h	/
145	MAJOR UPDATE: first version of D-Cache	ja_rd	4789d 07h	/
144	Added cache setup code to common startup code Important: the new cache won't work without this	ja_rd	4789d 07h	/
143	'adventure' sample by default will log from 0xb0000000 and simulation length is now longer	ja_rd	4790d 21h	/
142	'Adventure' bootstrap code now enables the cache (and runs noticeably faster on DE-1 board)	ja_rd	4790d 21h	/
141	BUG FIX in cache: cpu stall logic was missing key case 2nd SW in a (cached) row was not being stalled	ja_rd	4790d 21h	/
140	BUG FIX in cpu: MTCx was using Rs as source instead of Rt BUG FIX in cpu: cached sequences of S* were failing, byte_we logic was wrong	ja_rd	4790d 21h	/
139	updated simulation & synthesis pre-generated entities ('hello' code sample)	ja_rd	4791d 14h	/
138	updated simulation & synthesis pre-generated entities ('hello' code sample)	ja_rd	4791d 14h	/
137	Updated TB2 for new cache interface ('unmapped' signal)	ja_rd	4791d 14h	/
136	Added debug output to synthesizable MPU template, and connected debug signals to LEDs	ja_rd	4791d 15h	/
135	Added debug output to synthesizable MPU template.	ja_rd	4791d 15h	/
134	Added 'unmapped access' flag to CPU core, meant for debug mostly. Eventually this flag will trigger an interrupt.	ja_rd	4791d 15h	/
133	First draft of the SDRAM controller (Still unused in the code working base)	ja_rd	4794d 12h	/
132	Fixed bug in stall logic (stall for back-to-back SW instructions was wrong)	ja_rd	4794d 12h	/
131	change to local system-dependent directory path	ja_rd	4794d 12h	/
130	typo fix	ja_rd	4794d 12h	/
129	updated pregenerated demo ('hello')	ja_rd	4794d 12h	/
128	updated precompiled simulation testbench	ja_rd	4794d 12h	/
127	added SDRAM verilog simulation model to sim script	ja_rd	4794d 12h	/
126	added SDRAM verilog simulation model	ja_rd	4794d 12h	/

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