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246 Added a SD-card bootloader demo.
Now we can load binaries from the DE-1 board SD interface.
This saves time because we no longer have to resynthesize the core to try new software. AND we can now run from 16-bit RAM, which should be faster than 8-bit flash...		 ja_rd 4261d 03h /
245 Modified 'Adventure' demo: added a make target to build a 'bootloadable' version of the binary.
The new binary ('code.bin') can be loaded and run from RAM at address 0x0 using the sdboot demo bootloader.		 ja_rd 4261d 03h /
244 New link script that puts everything on XRAM (16-bit SRAM on the DE-1 board).
Programs linked with this script will have to be 'bootloaded' on RAM.		 ja_rd 4261d 04h /
243 Added a port of ElmChan's FatFS library for the DE-1 board.
Uses bit-banged SPI interface so it should be trivially easy to port to other boards.		 ja_rd 4261d 04h /
242 BUG FIX:
The CPU was sometimes fetching a spurious opcode in the 1st cycle after a reset.
The cache now has a 'cache_ready' output which the CPU uses to know when NOT to update its IR.		 ja_rd 4261d 05h /
241 Updated simulation and synthesis object code packages with latest build of 'hello' minidemo. ja_rd 4261d 05h /
240 Added a few comments and minor changes to the DE-1 top entity. ja_rd 4261d 05h /
239 Fixed simulation script: the test bench does not need to use the obj code package, all it needs is in the simulation parameters package, including the code. ja_rd 4261d 05h /
238 BUG FIX: C startup code that copied initialized data to data section was wrong when initialized data was not a multiple of 4 bytes. ja_rd 4261d 09h /
237 Fixed test bench to work with latest modifications of SoC ja_rd 4261d 09h /
236 Added macros to SoC header file for easy access to GPIO registers ja_rd 4262d 05h /
235 Fixed comments in cache module ja_rd 4262d 05h /
234 Added a few GPIO registers to the SoC, updated the DE-1 'top' file to drive the SD interface with the GPIO signals. ja_rd 4262d 05h /
233 Fixed top entity for De-1 demos: Bootstrap BRAM size is now taken from a constant in the obj code package. ja_rd 4280d 17h /
232 Fixed bug in object code package generation.
This bug was causing spurious behaviors in the Hello demo.		 ja_rd 4280d 18h /
231 Updated file list ja_rd 4409d 09h /
230 Modelsim script updated to latest HW changes ja_rd 4409d 10h /
229 Code samples updated to use new VHDL config packages and new SoC (UART). ja_rd 4409d 10h /
228 SW simulator updated
Simulation of UART adapted to new hardware.
Added simulation of debug registers.		 ja_rd 4409d 10h /
227 Removed modules no longer used:
code_rom_pkg replaced by new package in SoC directory.
RS232 sub-modules replaced by new UART		 ja_rd 4409d 10h /
226 Updated demo and test bench to use new SoC entity. ja_rd 4409d 10h /
225 Added utility functions for the initialization of BRAM memories. ja_rd 4409d 10h /
224 MCU entity gutted and transformed into a SoC entity
Different UART, new generics...		 ja_rd 4409d 11h /
223 MCU entity renamed to SoC, moved to separate SoC directory ja_rd 4409d 11h /
222 Documentation updated ja_rd 4409d 11h /
221 Documentation updated ja_rd 4409d 11h /
220 New script for configuration package generation.
New directory for all utility scripts		 ja_rd 4409d 20h /
219 Added windows binary for MIPS simulator 'slite' to the SVN repo, for convenience. ja_rd 4410d 04h /
218 UART bug fix: rx_rdy flag must be clear only when reading the rx buffer ja_rd 4413d 10h /
217 Removed another SoC file prematurely committed ja_rd 4420d 00h /

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