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Rev Log message Author Age Path
85 BUG FIX: log2 function was wrong ja_rd 4898d 14h /
84 Added 'trigger address' for file logging to both the
vhdl TB and the python script		 ja_rd 4898d 14h /
83 BUG FIX: LHU was not doing sign extension properly
BUG FIX: SLTIU decoding was wrong		 ja_rd 4898d 14h /
82 bug fix: SLTI wasn't working properly in some cases ja_rd 4900d 14h /
81 Added a wait state to the SRAM area for the DE-1 demo code ja_rd 4907d 09h /
80 Stub cache fixed
Now supports code refills from static 16- and 8- bit memory
Plus many mirror corrections		 ja_rd 4907d 09h /
79 modelsim wave window script updated ja_rd 4908d 11h /
78 Code sample 'memtest' adapted to test read from flash ja_rd 4908d 11h /
77 Simulation template now supports simulated flash
Synthesis template adapted to latest cache interface
Python script now supports simulated flash		 ja_rd 4908d 11h /
76 Adapted pregenerated vhdl files to latest changes ja_rd 4908d 12h /
75 Added support for 8-bit-wide static memory (e.g. Flash)
Updated demo 'top' file to use the DE-1 onboard flash		 ja_rd 4908d 12h /
74 Fixed (harmless) error in simulation template 2 ja_rd 4908d 16h /
73 Fixed comment about write cycles in cache module ja_rd 4908d 16h /
72 Fixed stupid bug in SRAM write cycles (setup time violated)
Wait states implemented for SRAM wait and read cycles		 ja_rd 4908d 16h /
71 Doc updated to reflect last changes ja_rd 4909d 04h /
70 updated CodeBlocks project file ja_rd 4909d 04h /
69 Updated simulation scripts
Obsolete sim script removed		 ja_rd 4909d 04h /
68 Updated pre-generated vhdl files ja_rd 4909d 04h /
67 Deprecated files:
Marked three files as unused, to be removed		 ja_rd 4909d 04h /
66 Code samples:
Updated all code samples to use TB2 template and new memory map		 ja_rd 4909d 04h /
65 Fixed io input mux in MPU template 1 ja_rd 4909d 04h /
64 Refactored memory decoding logic
(wait states and read-only attributes unimplemented yet)		 ja_rd 4909d 04h /
63 DE-1 demo top module:
added registers for SD interface, switches and 7-seg display		 ja_rd 4909d 04h /
62 CPU fixed:
fixed bug in EPC load logic relative to mem_wait stalls
parametrized reset and trap vector addresses		 ja_rd 4909d 04h /
61 SW simulator updated:
new mips-1 memory map and trap addresses
slightly better command line argument parsing		 ja_rd 4909d 04h /
60 Forgot to upload new TB package!!
Without this, simulations don't work...		 ja_rd 4909d 04h /
59 cleaned up top vhdl module of demo
moved reset sync ff chain to top module
updated pre-generated demo file		 ja_rd 4910d 18h /
58 Cleaned up cache stub code ja_rd 4911d 05h /
57 updated precompiled demo:
single 32-bit BROM instead of 4x8-bit		 ja_rd 4911d 06h /
56 synthesis mpu template updated:
BRAM is now one 32-bit-wide block instead of 4 8-bitters
(it is read only)
python script updated accordingly		 ja_rd 4911d 06h /

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