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Rev Log message Author Age Path
38 Reduced processing latency of Huffman encoding mikel262 5597d 01h /
37 Replaced VHDL Header RAM with Verilog, initialized via readmemh from hex file. mikel262 5601d 05h /
36 Fixed RLE ZRL bug. Added Chrominance Huffman tables. Fixed num encoded bytes bug. mikel262 5603d 01h /
35 Added check for image width in testbench. mikel262 5603d 13h /
34 Moved Quantizer to separate pipeline stage to balance processing chain load. mikel262 5603d 21h /
33 mikel262 5604d 06h /
32 mikel262 5605d 01h /
31 Specification update, minor area improvements in BUF_FIFO. mikel262 5608d 02h /
30 mikel262 5608d 15h /
29 mikel262 5608d 22h /
28 BU_FIFO SUB_RAM is now monolithic single block used by all SubFIFO - effect much less memory block usage. mikel262 5608d 23h /
27 mikel262 5611d 11h /
26 mikel262 5611d 12h /
25 moved from branch to trunk mikel262 5611d 12h /
24 mikel262 5611d 12h /
23 mikel262 5612d 22h /
22 Changed divider to use reciprocal lookup table. Improved Huffman processing time. BUF_FIFO almost full signal modified. mikel262 5613d 23h /
21 Huffman.vhd processing latency shortened. mikel262 5614d 22h /
20 Added compressed JPEG output file from testbench mikel262 5614d 23h /
19 Timing improved in MDCT and in Huffman mikel262 5615d 01h /
18 Huffman old design restored. Simulation HOWTO added. mikel262 5615d 01h /
17 return to original version, better timing, smaller area but higher processing time mikel262 5615d 22h /
16 Huffman timing improved mikel262 5615d 22h /
15 mikel262 5616d 01h /
14 timing improve mikel262 5616d 23h /
13 Timing improvements mikel262 5616d 23h /
12 Fix Quartus synthesis error and timing problem in Huffman.vhd mikel262 5618d 07h /
11 mikel262 5619d 02h /
10 missing file added mikel262 5619d 02h /
9 mikel262 5619d 04h /

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