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Rev Log message Author Age Path
38 Reduced processing latency of Huffman encoding mikel262 5573d 17h /
37 Replaced VHDL Header RAM with Verilog, initialized via readmemh from hex file. mikel262 5577d 21h /
36 Fixed RLE ZRL bug. Added Chrominance Huffman tables. Fixed num encoded bytes bug. mikel262 5579d 17h /
35 Added check for image width in testbench. mikel262 5580d 05h /
34 Moved Quantizer to separate pipeline stage to balance processing chain load. mikel262 5580d 14h /
33 mikel262 5580d 22h /
32 mikel262 5581d 18h /
31 Specification update, minor area improvements in BUF_FIFO. mikel262 5584d 19h /
30 mikel262 5585d 07h /
29 mikel262 5585d 15h /
28 BU_FIFO SUB_RAM is now monolithic single block used by all SubFIFO - effect much less memory block usage. mikel262 5585d 15h /
27 mikel262 5588d 04h /
26 mikel262 5588d 04h /
25 moved from branch to trunk mikel262 5588d 04h /
24 mikel262 5588d 04h /
23 mikel262 5589d 14h /
22 Changed divider to use reciprocal lookup table. Improved Huffman processing time. BUF_FIFO almost full signal modified. mikel262 5590d 15h /
21 Huffman.vhd processing latency shortened. mikel262 5591d 15h /
20 Added compressed JPEG output file from testbench mikel262 5591d 16h /
19 Timing improved in MDCT and in Huffman mikel262 5591d 18h /
18 Huffman old design restored. Simulation HOWTO added. mikel262 5591d 18h /
17 return to original version, better timing, smaller area but higher processing time mikel262 5592d 14h /
16 Huffman timing improved mikel262 5592d 15h /
15 mikel262 5592d 17h /
14 timing improve mikel262 5593d 15h /
13 Timing improvements mikel262 5593d 16h /
12 Fix Quartus synthesis error and timing problem in Huffman.vhd mikel262 5594d 23h /
11 mikel262 5595d 18h /
10 missing file added mikel262 5595d 19h /
9 mikel262 5595d 21h /

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