URL https://opencores.org/ocsvn/mlite/mlite/trunk

Subversion Repositories mlite

[/] - Rev 288

Rev	Log message	Author	Age	Path
288	Added Ethernet MAC with DMA	rhoads	6035d 11h	/
287	Added ethernet and flash control	rhoads	6035d 12h	/
286	Added eth_dma	rhoads	6035d 12h	/
285	Added eth_dma	rhoads	6035d 13h	/
284	Removed unsupported branch likely opcodes	rhoads	6035d 13h	/
283	Don't re-display menu if invalid key received	rhoads	6052d 11h	/
282	Removed DDR read loop in idle thread	rhoads	6052d 11h	/
281	Fix IP packet buffer leak	rhoads	6052d 12h	/
280	Fix comment	rhoads	6052d 12h	/
279	Expand read buffer size to two characters	rhoads	6052d 12h	/
278	Fix refresh bug	rhoads	6052d 12h	/
277	Permit 1MB files to be downloaded	rhoads	6056d 12h	/
276	In idle thread loop through DDR memory	rhoads	6056d 12h	/
275	Better error recovery if bad key received	rhoads	6056d 12h	/
274	Prevent strncat from being an intrinsic function	rhoads	6056d 12h	/
273	For DDR support	rhoads	6074d 00h	/
272	Added target for DDR development	rhoads	6078d 21h	/
271	Moved print_hex() to no_os.c	rhoads	6078d 21h	/
270	Added print_hex	rhoads	6078d 21h	/
269	Permit binary file to be sent	rhoads	6078d 21h	/
268	Initialize DDR chip	rhoads	6078d 21h	/
267	Added call to DdrInit()	rhoads	6078d 21h	/
266	Show image size in hexidecimal	rhoads	6078d 21h	/
265	Changed write_byte_enable to byte_we	rhoads	6078d 21h	/
264	Latch address and byte_we in mem_ctrl.vhd	rhoads	6078d 21h	/
263	Changed write_byte_enable to byte_we	rhoads	6078d 21h	/
262	Changed comment	rhoads	6078d 22h	/
261	Removed commented out lines	rhoads	6078d 22h	/
260	Removed Xilinx use statements	rhoads	6078d 22h	/
259	Support for DDR	rhoads	6078d 22h	/