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Subversion Repositories mod_sim_exp

[/] - Rev 85

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Rev	Log message	Author	Age	Path
85	changed so that reset now also affects slave register	JonasDC	4094d 04h	/
84	AXI-Lite interface updated, now tested and verified on Xilinx FPGA renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS	JonasDC	4095d 13h	/
83	now using values from mod_sim_exp_pkg instead of direct entity	JonasDC	4097d 14h	/
82	added first version of axi-lite interface and testbench for basic axi-lite operations, now under test	JonasDC	4114d 10h	/
81	updated files, now using the components of the mod_sim_exp_pkg instead of direct entity declaration	JonasDC	4114d 10h	/
80	renamed to version 1.1 to follow the versioning system	JonasDC	4124d 03h	/
79	Tag for version 1.3 (with new ram style	JonasDC	4124d 04h	/
78	updated documentation with new RAM style information	JonasDC	4124d 04h	/
77	found fault in code, now synthesizes normally	JonasDC	4130d 01h	/
76	testbench update	JonasDC	4132d 12h	/
75	made rw_address a vector of a fixed width	JonasDC	4132d 12h	/
74	removed C_NR_OP and C_NR_M from the generic of mod_sim_exp_core and made them contstants, because currently no other values than 4 an 2 resp. are supported/can be implemented.	JonasDC	4135d 08h	/
73	updated plb interface, mem_style and device generics added	JonasDC	4136d 07h	/
72	deleted old resources	JonasDC	4137d 07h	/
71	added synthesis report for altera and xilinx for the new ram. added coregen sources for xilinx for primitive RAM	JonasDC	4137d 07h	/
70	updated testbench for use with new core parameters updated makefile, added new sources	JonasDC	4137d 08h	/
69	big update, the mod_sim_exp core now has a selectable ram structure. a generic ram that should be usable in any fpga, a asymmetric ram that is usable for some devices of altera or xilinx and uses less resources.	JonasDC	4137d 08h	/
68	branch no longer needed	JonasDC	4137d 10h	/
67	added memory modules for modulus and operands for FPGA's that support asymmetric memory inferring.	JonasDC	4137d 11h	/
66	added asymmetric ram structures to support a more performant ramstyle. defined for xilinx and altera, not tested with other tools.	JonasDC	4137d 11h	/
65	updated plb interface, now modulus is selectable and, fifo depth is adjustable. updated makefile with new sources and update component in package	JonasDC	4145d 03h	/
64	added synthesis reports of xilinx and altera	JonasDC	4145d 08h	/
63	now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx	JonasDC	4145d 08h	/
62	not used anymore	JonasDC	4145d 11h	/
61	updated comments, added optional altera constraint	JonasDC	4145d 11h	/
60	generic version of the fifo, not device specific anymore, uses dpram_generic updated comments of RAM templates.	JonasDC	4148d 01h	/
59	added templates that correctly infer RAM, for dual port en true dual port RAM added general functions file, (used in the two RAM templates)	JonasDC	4148d 02h	/
58	made fifo full a warning	JonasDC	4151d 02h	/
57	new fifo design, is now generic (verified with altera and xilinx) and uses block ram	JonasDC	4151d 02h	/
56	this is a branch to test performance of a new style of ram	JonasDC	4151d 04h	/

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[/] - Rev 85

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