| Rev |
Log message |
Author |
Age |
Path |
| 207 |
Added a simple 8-bit, fixed asynchronous serial interface with compile time settable bit-rate, parity enable, and parity mode generics. |
jshamlet |
1530d 19h |
/ |
| 206 |
Merged interrupt logic with other clocked process. |
jshamlet |
1534d 14h |
/ |
| 205 |
More code and comment cleanup for the new SDLC engine |
jshamlet |
1534d 14h |
/ |
| 204 |
Fixed more incorrect comments |
jshamlet |
1534d 15h |
/ |
| 203 |
Removed an extra delay FF from the bitclock rising edge signal for the clock slave configuration to better center the rising edge pulse on the receive signal. |
jshamlet |
1534d 21h |
/ |
| 202 |
Fixed receiver bug that caused false flag detection,
Split the large sdlc_serial_ctrl entity into sub-entities to make debugging easier. |
jshamlet |
1534d 22h |
/ |
| 201 |
Fixed comments regarding RX Checksum location |
jshamlet |
1536d 19h |
/ |
| 200 |
Renamed dual-port buffer to match other entities. |
jshamlet |
1536d 19h |
/ |
| 199 |
Added monitor ram for debugging and fixed issue with dual-port read path. |
jshamlet |
1536d 19h |
/ |
| 198 |
Removed debugging memory |
jshamlet |
1537d 03h |
/ |
| 197 |
Fixed incorrect comments |
jshamlet |
1537d 04h |
/ |
| 196 |
Modified the update logic to allow direct writes to offset 0xFE for refreshing the clock status. This way, any write to the clock status register will immediately be undone. (Writing 0x00 to offset 0xFF is once-more ignored) |
jshamlet |
1537d 04h |
/ |
| 195 |
Added dual-port RAM core for SDLC interface. |
jshamlet |
1537d 23h |
/ |
| 194 |
Cleaned up licensing sections |
jshamlet |
1537d 23h |
/ |
| 193 |
Fixed incorrect comment in o8_alu16.vhd. The value of the write to 0x1F doesn't matter, as the write itself triggers the calculation. |
jshamlet |
1538d 00h |
/ |
| 192 |
Added SDLC packet engine |
jshamlet |
1538d 00h |
/ |
| 191 |
Cleaned up comments, added back the OPEN8_NULLBUS constant, and added some new modules for ADCs and LCD displays.
Also made the button input module more configurable by moving the debounce code to a separate entity and using generics to instantiate it. |
jshamlet |
1538d 00h |
/ |
| 190 |
Fixed a bug in CPU where RTI/RTS wasn't idling the instruction cache, causing intermittent failures where RTI would execute as RTS, corrupting the stack;
Fixed a bug in the real-time clock where the uSec tick generator would stop if the PIT timer value was left/set to 0x00. |
jshamlet |
1549d 21h |
/ |
| 189 |
Merged changes from private repository,
added ceil_log2 function to Open8_pkg, since it is used to calculate RAM vectors,
cleaned up comments and removed local copies of the ceil_log2 function from peripherals. |
jshamlet |
1550d 22h |
/ |
| 188 |
Added a generic to alter the behavior of RTI so that it can optionally skip restoring the general purpose flags GP4 to GP7, allowing ISR's to make persistent changes to them. Also exported these flags to the top level for use outside the CPU. |
jshamlet |
1551d 01h |
/ |
| 187 |
Added the CPU_Halt input, only now as an input to the instruction decoder. The CPU_Halt line will assert the registered CPU_Halt_Req, which will cause the instruction decoder to abort the current instruction, reset the PC, then enter a hold state until the line is deasserted. Additionally, a very minor bug that could cause the SMSK instruction to effectively execute twice if interrupted was fixed. Lastly, cleaned up the comments even more. |
jshamlet |
1552d 21h |
/ |
| 186 |
Merged the interrupt override logic into the case structure, simplifying how interrupts are processed. |
jshamlet |
1555d 21h |
/ |
| 185 |
1) Fixed an apparently long-standing bug where the interrupt bit wasn't being cleared after an RTI
2) Modified the program counter logic to be simpler. It now always increments, and states control the increment using the offset field. A new set of constants was added to replace the old states.
3) Modified the ALU to always use Operand1 instead of ALU_Ctrl.Data (and removed the field in the record). A new ALU command, ALU_GMSK, was added, as it was the only instruction to set the .Data field to something other than Operand1 (Int_Mask)
4) Modified the package file so that flag names match what the assembler calls them. FL_Z is now PSR_Z, FL_GP1 is now PSR_GP4, etc.
5) Cleaned up the comments and code formatting |
jshamlet |
1556d 00h |
/ |
| 184 |
More file/entity renaming to match private versions. |
jshamlet |
1557d 23h |
/ |
| 183 |
Renamed core to o8_cpu to match new naming scheme |
jshamlet |
1558d 00h |
/ |
| 182 |
Simplified the address generation logic at the expense of making LDX take one additional clock cycle. This allowed the address logic to be split out of the main state machine and simplified (greatly). During this process, a bug in SDO was found and fixed that caused it to return through the wrong pipe fill state wnen auto increment was disabled. |
jshamlet |
1558d 00h |
/ |
| 181 |
Altered the RSP instruction to allow the stack pointed to either be restored from registers or stored to registers based on the status of a processor bit. Also modified LDX to simplify the address logic. |
jshamlet |
1558d 20h |
/ |
| 180 |
Added additional Open8 compatible modules |
jshamlet |
1563d 00h |
/ |
| 179 |
Replacing files accidentally deleted during check-in |
jshamlet |
1572d 20h |
/ |
| 178 |
Adding Open8 toolset for pure assembly |
jshamlet |
1572d 20h |
/ |
