| Rev |
Log message |
Author |
Age |
Path |
| 209 |
Fixed an issue in the PIT timer that caused an immediate interrupt on interval write,
Fixed an issue in the epoch timer that resulted in a spurious interrupt due to extra LSB's being set by default in the set point register,
While cleaning elsewhere, founding a spacing issue in the CPU HDL,
Added a 4k ROM and MW core. |
jshamlet |
1546d 20h |
/ |
| 208 |
Removed unnecessary package references |
jshamlet |
1547d 06h |
/ |
| 207 |
Added a simple 8-bit, fixed asynchronous serial interface with compile time settable bit-rate, parity enable, and parity mode generics. |
jshamlet |
1547d 23h |
/ |
| 206 |
Merged interrupt logic with other clocked process. |
jshamlet |
1551d 18h |
/ |
| 205 |
More code and comment cleanup for the new SDLC engine |
jshamlet |
1551d 18h |
/ |
| 204 |
Fixed more incorrect comments |
jshamlet |
1551d 18h |
/ |
| 203 |
Removed an extra delay FF from the bitclock rising edge signal for the clock slave configuration to better center the rising edge pulse on the receive signal. |
jshamlet |
1552d 00h |
/ |
| 202 |
Fixed receiver bug that caused false flag detection,
Split the large sdlc_serial_ctrl entity into sub-entities to make debugging easier. |
jshamlet |
1552d 01h |
/ |
| 201 |
Fixed comments regarding RX Checksum location |
jshamlet |
1553d 22h |
/ |
| 200 |
Renamed dual-port buffer to match other entities. |
jshamlet |
1553d 22h |
/ |
| 199 |
Added monitor ram for debugging and fixed issue with dual-port read path. |
jshamlet |
1553d 23h |
/ |
| 198 |
Removed debugging memory |
jshamlet |
1554d 07h |
/ |
| 197 |
Fixed incorrect comments |
jshamlet |
1554d 07h |
/ |
| 196 |
Modified the update logic to allow direct writes to offset 0xFE for refreshing the clock status. This way, any write to the clock status register will immediately be undone. (Writing 0x00 to offset 0xFF is once-more ignored) |
jshamlet |
1554d 07h |
/ |
| 195 |
Added dual-port RAM core for SDLC interface. |
jshamlet |
1555d 02h |
/ |
| 194 |
Cleaned up licensing sections |
jshamlet |
1555d 02h |
/ |
| 193 |
Fixed incorrect comment in o8_alu16.vhd. The value of the write to 0x1F doesn't matter, as the write itself triggers the calculation. |
jshamlet |
1555d 03h |
/ |
| 192 |
Added SDLC packet engine |
jshamlet |
1555d 03h |
/ |
| 191 |
Cleaned up comments, added back the OPEN8_NULLBUS constant, and added some new modules for ADCs and LCD displays.
Also made the button input module more configurable by moving the debounce code to a separate entity and using generics to instantiate it. |
jshamlet |
1555d 03h |
/ |
| 190 |
Fixed a bug in CPU where RTI/RTS wasn't idling the instruction cache, causing intermittent failures where RTI would execute as RTS, corrupting the stack;
Fixed a bug in the real-time clock where the uSec tick generator would stop if the PIT timer value was left/set to 0x00. |
jshamlet |
1567d 01h |
/ |
| 189 |
Merged changes from private repository,
added ceil_log2 function to Open8_pkg, since it is used to calculate RAM vectors,
cleaned up comments and removed local copies of the ceil_log2 function from peripherals. |
jshamlet |
1568d 01h |
/ |
| 188 |
Added a generic to alter the behavior of RTI so that it can optionally skip restoring the general purpose flags GP4 to GP7, allowing ISR's to make persistent changes to them. Also exported these flags to the top level for use outside the CPU. |
jshamlet |
1568d 04h |
/ |
| 187 |
Added the CPU_Halt input, only now as an input to the instruction decoder. The CPU_Halt line will assert the registered CPU_Halt_Req, which will cause the instruction decoder to abort the current instruction, reset the PC, then enter a hold state until the line is deasserted. Additionally, a very minor bug that could cause the SMSK instruction to effectively execute twice if interrupted was fixed. Lastly, cleaned up the comments even more. |
jshamlet |
1570d 00h |
/ |
| 186 |
Merged the interrupt override logic into the case structure, simplifying how interrupts are processed. |
jshamlet |
1573d 00h |
/ |
| 185 |
1) Fixed an apparently long-standing bug where the interrupt bit wasn't being cleared after an RTI
2) Modified the program counter logic to be simpler. It now always increments, and states control the increment using the offset field. A new set of constants was added to replace the old states.
3) Modified the ALU to always use Operand1 instead of ALU_Ctrl.Data (and removed the field in the record). A new ALU command, ALU_GMSK, was added, as it was the only instruction to set the .Data field to something other than Operand1 (Int_Mask)
4) Modified the package file so that flag names match what the assembler calls them. FL_Z is now PSR_Z, FL_GP1 is now PSR_GP4, etc.
5) Cleaned up the comments and code formatting |
jshamlet |
1573d 03h |
/ |
| 184 |
More file/entity renaming to match private versions. |
jshamlet |
1575d 02h |
/ |
| 183 |
Renamed core to o8_cpu to match new naming scheme |
jshamlet |
1575d 03h |
/ |
| 182 |
Simplified the address generation logic at the expense of making LDX take one additional clock cycle. This allowed the address logic to be split out of the main state machine and simplified (greatly). During this process, a bug in SDO was found and fixed that caused it to return through the wrong pipe fill state wnen auto increment was disabled. |
jshamlet |
1575d 03h |
/ |
| 181 |
Altered the RSP instruction to allow the stack pointed to either be restored from registers or stored to registers based on the status of a processor bit. Also modified LDX to simplify the address logic. |
jshamlet |
1575d 23h |
/ |
| 180 |
Added additional Open8 compatible modules |
jshamlet |
1580d 03h |
/ |
