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Rev Log message Author Age Path
131 Update ChangeLog olivier.girard 4549d 22h /
130 Fixed POP.B bug (see Bugtracker http://opencores.org/bug,assign,2137 ) olivier.girard 4549d 22h /
129 Update ChangeLog olivier.girard 4625d 22h /
128 Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) olivier.girard 4625d 23h /
127 update changelog... olivier.girard 4661d 22h /
126 Remove freewrap642 directory.
Tools users now have to install TCL/TK instead.		 olivier.girard 4661d 22h /
125 update changelog... olivier.girard 4676d 01h /
124 Improved gdbproxy robustness.
Create a workaround to prevent GDB from freezing when single-stepping on a LPMx or a "JMP $-0" instruction.		 olivier.girard 4676d 12h /
123 update changelog... olivier.girard 4697d 23h /
122 Add coverage report generation (NCVERILOG only)
Add support for the ISIM Xilinx simulator.		 olivier.girard 4697d 23h /
121 Add a new FPGA example for the LX9 Microboard from Avnet.
Many thanks to Ricardo Ribalda Delgado for his contribution on this one :-)		 olivier.girard 4769d 23h /
120 update tools changelog... olivier.girard 4801d 06h /
119 Slight improvement of the gdbproxy to improve the support of the EMBSYSREGVIEW Eclipse plugin. olivier.girard 4801d 07h /
118 Changelog update (move to modified BSD license). olivier.girard 4802d 00h /
117 To facilitate commercial adoption of the openMSP430, the core has moved to a modified BSD license. olivier.girard 4802d 00h /
116 Update documentation to reflect the latest core updates. olivier.girard 4818d 00h /
115 Add linker script example. olivier.girard 4827d 00h /
114 Improved the VerifyCPU_ID procedure. olivier.girard 4829d 23h /
113 Created ChangeLog files... olivier.girard 4831d 00h /
112 Modified comment. olivier.girard 4834d 23h /
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4835d 23h /
110 Rework of the GUI for the software development tools.
Added possibility to give custom information through the omsp_alias.xml file.		 olivier.girard 4836d 23h /
109 Update Xilinx FPGA example with the latest openMSP430 core RTL version. olivier.girard 4890d 08h /
108 Add serial debug interface tasks to the Actel fpga simulation environment. olivier.girard 4891d 21h /
107 Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version. olivier.girard 4891d 21h /
106 Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).		 olivier.girard 4891d 22h /
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.		 olivier.girard 4906d 22h /
104 Update all FPGA example projects with the latest RTL version. olivier.girard 4911d 00h /
103 Removed the timescale from all RTL files.
Added possibility to exclude the "includes" statements from the RTL.		 olivier.girard 4912d 05h /
102 Fixed bug reported by Mihai ( http://opencores.org/bug,view,1955 ).
The following PUSH instructions are now working as expected:

- indexed mode: PUSH x(R1)
- indirect register mode: PUSH @R1
- indirect autoincrement: PUSH @R1+		 olivier.girard 4912d 22h /

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