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57 Update design to exclude the range mode from the debug hardware breakpoint units. As this feature is not used by GDB, it has been disabled in order to improve the timings and save a bit of area/utilisation.
Note that if required, this feature can be re-enabled through the `HWBRK_RANGE define located in the "openMSP430_defines.v" file.		 olivier.girard 5301d 09h /
56 Update Design Compiler Synthesis scripts. olivier.girard 5305d 16h /
55 Add a "sandbox" test pattern to play around with the simulation :-P olivier.girard 5306d 11h /
54 Update FPGA projects with the combinatorial loop fixed. olivier.girard 5306d 14h /
53 Fixed the following combinatorial timing loop:
1- irq_detect (omsp_frontend)
2- decode (omsp_frontend)
3- dbg_swbrk (omsp_dbg)
4- halt_flag_set (omsp_dbg)
6- dbg_halt_cmd (omsp_dbg)
7- irq_detect (omsp_frontend)

Without this fix, problem could occur whenever an IRQ request arrives during a software breakpoint instruction fetch.		 olivier.girard 5306d 14h /
52 Re-add pdf documentation. olivier.girard 5311d 10h /
51 Re-add open-office documentation. olivier.girard 5311d 10h /
50 Re-add html documentation. olivier.girard 5311d 10h /
49 Temporar documentation removal because of broken SVN update. olivier.girard 5311d 10h /
48 Re-add html documentation. olivier.girard 5311d 10h /
47 Temporar documentation removal because of broken SVN update. olivier.girard 5311d 10h /
46 Re-add html documentation. olivier.girard 5311d 10h /
45 Temporar documentation removal because of broken SVN update. olivier.girard 5311d 10h /
44 Update documentation with the "Integration and Connectivity" section. olivier.girard 5311d 11h /
43 Re-add documentation (earlier pdf was broken). olivier.girard 5335d 10h /
42 olivier.girard 5335d 10h /
41 Update bitstream & SVN ignore patterns. olivier.girard 5335d 10h /
40 Minor updates. olivier.girard 5335d 11h /
39 Update FPGA projects with new openMSP430 core. olivier.girard 5335d 11h /
38 Remove old core version. olivier.girard 5335d 11h /
37 olivier.girard 5335d 11h /
36 Remove old core version. olivier.girard 5335d 12h /
35 Update documentation to reflect the latest Verilog changes. olivier.girard 5335d 12h /
34 To avoid potential conflicts with other Verilog modules in bigger projects, the openMSP430 sub-modules have all been renamed with the "omsp_" prefix. olivier.girard 5335d 13h /
33 In order to avoid confusion, the following changes have been implemented to the Verilog code:
- renamed the "rom_*" ports and defines to "pmem_*" (program memory).
- renamed the "ram_*" ports and defines to "dmem_*" (data memory).

In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.		 olivier.girard 5335d 14h /
32 Minor update to the HTML documentation + add some SVN ignore properties to the Altera FPGA project simulation directory. olivier.girard 5337d 10h /
31 Update documentation (new Altera FPGA project + diverse minor updates) olivier.girard 5337d 11h /
30 Add Altera Cyclone II FPGA project example (thanks to Vadim Akimov contribution). olivier.girard 5337d 11h /
29 Add Altera Cyclone II FPGA project example. olivier.girard 5337d 12h /
28 renamed "diligent_s3board" directory to "xilinx_diligent_s3board" olivier.girard 5345d 20h /

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