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Subversion Repositories openmsp430

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Rev	Log message	Author	Age	Path
85	Diverse RTL cosmetic updates.	olivier.girard	4929d 10h	/
84	Update SRAM model in the core testbench to prevent the IEEE warning when running simulations. Update watchdog to fix NMI synchronisation problem. Add synchronizers for the PUC signal in the debug interface.	olivier.girard	4934d 11h	/
83	Add Oscilloscope screenshot + link to the original game.	olivier.girard	4980d 11h	/
82	Update Actel example project: - synthesis scripts. - Spacewar demo program. - SVN ignore patterns for diverse directories	olivier.girard	4980d 11h	/
81	Initial synthesis, P&R setup for the Actel example project.	olivier.girard	4983d 09h	/
80	Create initial version of the Actel FPGA implementation example.	olivier.girard	4983d 18h	/
79	Update the GPIO peripheral to fix a potential synchronization issue.	olivier.girard	4995d 12h	/
78	update windows executable files	olivier.girard	4997d 11h	/
77	Tool script update with additional checks: - execution of the "msp430-objcopy" ran properly - add a timeout delay to wait for the generated bin file - check if the size of the ELF file program section is the same as the available program memory.	olivier.girard	4997d 11h	/
76	Add possibility to simulate C code within the "core" environment.	olivier.girard	5000d 10h	/
75	Update development tools windows executable to support memories whose size are not a power of 2.	olivier.girard	5082d 10h	/
74	Update serial debug interface to support memories with a size which is not a power of 2. Update the software tools accordingly.	olivier.girard	5082d 11h	/
73	Update all bash scripts headers with "#!/bin/bash" instead of "#!/bin/sh". This will prevent compatibility problems in systems where bash isn't the default shell.	olivier.girard	5107d 12h	/
72	Expand configurability options of the program and data memory sizes.	olivier.girard	5109d 12h	/
71	Update the FPGA example projects with the newer openMSP430 core including the hardware multiplier.	olivier.girard	5256d 11h	/
70	Add Area and Speed documentation.	olivier.girard	5256d 14h	/
69	Update HTML documentation with 16x16 hardware multiplier info.	olivier.girard	5256d 18h	/
68	Update synthesis scripts with the hardware multiplier support.	olivier.girard	5256d 19h	/
67	Added 16x16 Hardware Multiplier.	olivier.girard	5256d 19h	/
66	The peripheral templates are now under BSD license. Developers of new peripherals based on these templates won't have to disclose their code.	olivier.girard	5256d 23h	/
65	Add possibility to disable waveform dumping by setting the OMSP_NODUMP environment variable to 1.	olivier.girard	5267d 09h	/
64	Add Actel synthesis environment for size and speed analysis.	olivier.girard	5277d 19h	/
63	Add Altera synthesis environment for size and speed analysis.	olivier.girard	5277d 19h	/
62	Add Xilinx synthesis environment for size&speed analysis.	olivier.girard	5277d 21h	/
61	Update openMSP430 rtl.	olivier.girard	5288d 09h	/
60	Cleanup of the PC (R0) generation logic. Formal equivalence was shown between the new and old code with Synopsys' Formality (to make sure that nothing has been broken :-P ).	olivier.girard	5288d 10h	/
59	Update the FPGA projects with the latest core design updates.	olivier.girard	5290d 08h	/
58	Update the debug hardware breakpoint verification patterns to reflect the latest design updates.	olivier.girard	5290d 08h	/
57	Update design to exclude the range mode from the debug hardware breakpoint units. As this feature is not used by GDB, it has been disabled in order to improve the timings and save a bit of area/utilisation. Note that if required, this feature can be re-enabled through the `HWBRK_RANGE define located in the "openMSP430_defines.v" file.	olivier.girard	5290d 08h	/
56	Update Design Compiler Synthesis scripts.	olivier.girard	5294d 15h	/

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[/] - Rev 85

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