OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] - Rev 628

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
628 orpsoc: add Digilent Atlys spartan6 board Makefiles

Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
stekern 4680d 19h /
627 orpsoc: add Digilent Atlys spartan6 board rtl

Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
stekern 4680d 19h /
626 Fix to support GCC 4.6 by disabling -Werror. jeremybennett 4689d 10h /
625 Fixed configuration to work with GCC 4.6, added -Werror to avoid GCC 4.6 warning as a temporary fix. Added pic.cfg to EXTRA_DIST. Made tests build with SILENT_RULES if available. jeremybennett 4689d 11h /
624 add missing delay slot instruction
vPortDisableInterrupts
vPortEnableInterrupts
filepang 4690d 15h /
623 cleanup source code
Demo/OpenRISC_SIM_GCC/arch/support.h
Demo/OpenRISC_SIM_GCC/arch/interrupts.h
Demo/OpenRISC_SIM_GCC/arch/link.ld

add gpio driver

add gpio base address definition
filepang 4691d 07h /
622 update uart driver for support multiple uart cores
from http://opencores.org/ocsvn/openrisc/openrisc/trunk/orpsocv2/sw/drivers/uart
filepang 4691d 09h /
621 update sim.cfg for newer version of Or1ksim.
remove unused files.
cleanup source code.

insert non-local jump(setjmp) in xPortStartScheduler. now xPortStartScheduler() will
be returned by xPortEndScheduler().
filepang 4693d 01h /
620 remove unused file
cleanup makefile
update uart_init(), disable interrupt before initialize.
jeremybennett 4693d 14h /
619 ORPSoC OR1200 fix and regression test for bug 51.

signed-off Julius Baxter
reviewed by Stefan Kristiansson
julius 4702d 01h /
618 Remove unused parameter Tp olof 4702d 09h /
617 Set tx_negedge correctly (Fixes bug #12) olof 4706d 12h /
616 Initial port of FreeRTOS by filepang (Kim Sung Su). jeremybennett 4707d 10h /
615 Initial port of FreeRTOS by filepang (Kim Sung Su). jeremybennett 4707d 10h /
614 Initial port of FreeRTOS by filepang (Kim Sung Su). jeremybennett 4707d 10h /
613 Initial port of FreeRTOS by filepang (Kim Sung Su). jeremybennett 4707d 10h /
612 Initial port of FreeRTOS by filepang (Kim Sung Su). jeremybennett 4707d 10h /
611 Initial port of FreeRTOS by filepang (Kim Sung Su). jeremybennett 4707d 10h /
610 Initial port of FreeRTOS by filepang (Kim Sung Su). jeremybennett 4707d 10h /
609 Initial port of FreeRTOS by filepang (Kim Sung Su). jeremybennett 4707d 10h /
608 Initial port of FreeRTOS by filepang (Kim Sung Su). jeremybennett 4707d 10h /
607 Initial port of FreeRTOS by filepang (Kim Sung Su). jeremybennett 4707d 10h /
606 Initial port of FreeRTOS by filepang (Kim Sung Su). jeremybennett 4707d 10h /
605 Initial port of FreeRTOS by filepang (Kim Sung Su). jeremybennett 4707d 10h /
604 Initial port of FreeRTOS by filepang (Kim Sung Su). jeremybennett 4707d 10h /
603 Initial port of FreeRTOS by filepang (Kim Sung Su). jeremybennett 4707d 10h /
602 Initial port of FreeRTOS by filepang (Kim Sung Su). jeremybennett 4707d 10h /
601 Initial port of FreeRTOS by filepang (Kim Sung Su). jeremybennett 4707d 10h /
600 Initial port of FreeRTOS by filepang (Kim Sung Su). jeremybennett 4707d 10h /
599 Initial port of FreeRTOS by filepang (Kim Sung Su). jeremybennett 4707d 10h /

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.