| Rev |
Log message |
Author |
Age |
Path |
| 63 |
Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. |
julius |
5279d 23h |
/ |
| 62 |
This material is part of the separate website downloads directory. |
jeremybennett |
5291d 02h |
/ |
| 61 |
The build directory should not be part of the SVN configuration. |
jeremybennett |
5291d 03h |
/ |
| 60 |
Mark Jarvin's patches to support Mac OS X (Snow Leopard). |
jeremybennett |
5297d 20h |
/ |
| 59 |
Toolchain install script gcc patch change and gdb configure change |
julius |
5318d 20h |
/ |
| 58 |
ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up |
julius |
5321d 19h |
/ |
| 57 |
ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words |
julius |
5326d 23h |
/ |
| 56 |
adding generic pll model to orpsoc |
julius |
5335d 01h |
/ |
| 55 |
Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk |
julius |
5337d 15h |
/ |
| 54 |
wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist |
julius |
5347d 22h |
/ |
| 53 |
Fixed incorrect commandline option for ORPSoC and main makefile setting |
julius |
5365d 23h |
/ |
| 52 |
ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation |
julius |
5366d 19h |
/ |
| 51 |
ORPSoCv2 updates: cycle accurate profiling, ELF loading |
julius |
5380d 21h |
/ |
| 50 |
Adding or32_funcs.S |
julius |
5381d 01h |
/ |
| 49 |
Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update |
julius |
5399d 15h |
/ |
| 48 |
Adds an initialization to keep GCC happy in jp1_ll_read_jp1. |
jeremybennett |
5399d 18h |
/ |
| 47 |
debug proxy speed increase, block transfers possible with cpu aslong as dbg_interface has appropriate change, usb chip reinit function, changed some of the retry code in the usb transfer functions |
julius |
5409d 02h |
/ |
| 46 |
debug interfaces now support byte and non-aligned accesses from gdb |
julius |
5415d 02h |
/ |
| 45 |
Orpsoc eth test fix and script error message update |
julius |
5422d 02h |
/ |
| 44 |
New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades |
julius |
5451d 02h |
/ |
| 43 |
Couple of fixes to ORPSoC, new linux patch version in toolchain script |
julius |
5474d 23h |
/ |
| 42 |
Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model |
julius |
5490d 20h |
/ |
| 41 |
Update to or1k top |
julius |
5493d 21h |
/ |
| 40 |
Added GDB server to verilog simulation via VPI and make target to build and run this model |
julius |
5495d 02h |
/ |
| 39 |
Adding OR debug proxy a makefile tweak for uClibc and toolchain install script update |
julius |
5499d 03h |
/ |
| 38 |
Adding binutils, gcc, uClibc patched source and patches |
julius |
5509d 02h |
/ |
| 37 |
Update to the toolchain script - uses gcc-core package now instead of complete gcc |
julius |
5509d 03h |
/ |
| 36 |
Better clean rule in makefile |
julius |
5509d 03h |
/ |
| 35 |
Download and patch files with README files updated to explain what is in the new repository |
jeremybennett |
5509d 20h |
/ |
| 34 |
Created directories for download and patch files and added README's explaining what is in each one. |
jeremybennett |
5509d 21h |
/ |
