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Rev Log message Author Age Path
67 New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory julius 5230d 14h /
66 Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software. julius 5250d 12h /
65 ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix julius 5254d 18h /
64 Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile. julius 5257d 13h /
63 Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. julius 5267d 10h /
62 This material is part of the separate website downloads directory. jeremybennett 5278d 13h /
61 The build directory should not be part of the SVN configuration. jeremybennett 5278d 14h /
60 Mark Jarvin's patches to support Mac OS X (Snow Leopard). jeremybennett 5285d 07h /
59 Toolchain install script gcc patch change and gdb configure change julius 5306d 07h /
58 ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up julius 5309d 06h /
57 ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words julius 5314d 10h /
56 adding generic pll model to orpsoc julius 5322d 12h /
55 Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk julius 5325d 02h /
54 wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist julius 5335d 09h /
53 Fixed incorrect commandline option for ORPSoC and main makefile setting julius 5353d 10h /
52 ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation julius 5354d 06h /
51 ORPSoCv2 updates: cycle accurate profiling, ELF loading julius 5368d 08h /
50 Adding or32_funcs.S julius 5368d 13h /
49 Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update julius 5387d 02h /
48 Adds an initialization to keep GCC happy in jp1_ll_read_jp1. jeremybennett 5387d 05h /
47 debug proxy speed increase, block transfers possible with cpu aslong as dbg_interface has appropriate change, usb chip reinit function, changed some of the retry code in the usb transfer functions julius 5396d 13h /
46 debug interfaces now support byte and non-aligned accesses from gdb julius 5402d 14h /
45 Orpsoc eth test fix and script error message update julius 5409d 13h /
44 New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades julius 5438d 13h /
43 Couple of fixes to ORPSoC, new linux patch version in toolchain script julius 5462d 10h /
42 Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model julius 5478d 07h /
41 Update to or1k top julius 5481d 08h /
40 Added GDB server to verilog simulation via VPI and make target to build and run this model julius 5482d 13h /
39 Adding OR debug proxy a makefile tweak for uClibc and toolchain install script update julius 5486d 14h /
38 Adding binutils, gcc, uClibc patched source and patches julius 5496d 13h /

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