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Rev Log message Author Age Path
1008 Import ivang 8010d 21h /
1007 Import ivang 8010d 21h /
1006 Import ivang 8010d 21h /
1005 Import ivang 8010d 21h /
1004 Now every ramdisk image should have init program. simons 8011d 06h /
1003 cuc temporary files are deleted upon exiting markom 8011d 06h /
1002 Now every ramdisk image should have init program. simons 8011d 06h /
1001 fixed load/store state machine verilog generation errors markom 8011d 06h /
1000 IC/DC cache enable routines fixed. simons 8011d 07h /
999 Now every ramdisk image should have init program. simons 8011d 08h /
998 added missing fout initialization markom 8011d 09h /
997 PRINTF should be used instead of printf; command redirection repaired markom 8011d 10h /
996 some minor bugs fixed markom 8012d 09h /
995 This commit was manufactured by cvs2svn to create tag 'rel_3'. 8012d 16h /
994 Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board. lampret 8012d 16h /
993 Fixed IMMU bug. lampret 8012d 16h /
992 A bug when cache enabled and bus error comes fixed. simons 8013d 02h /
991 Different memory controller. simons 8013d 02h /
990 Test is now complete. simons 8013d 02h /
989 c++ is making problems so, for now, it is excluded. simons 8014d 10h /
988 ORP architecture supported. simons 8015d 01h /
987 ORP architecture supported. simons 8015d 08h /
986 outputs out of function are not registered anymore markom 8015d 09h /
985 DTLB translation doesn't work on or1ksim when IC/DC enabled. lampret 8015d 21h /
984 Disable SB until it is tested lampret 8015d 21h /
983 First checkin lampret 8015d 23h /
982 Moved to sim/bin lampret 8015d 23h /
981 First checkin. lampret 8015d 23h /
980 Removed sim.tcl that shouldn't be here. lampret 8015d 23h /
979 Removed old test case binaries. lampret 8015d 23h /

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