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Rev Log message Author Age Path
411 acv uart testsuite now works (without modem test) markom 8352d 03h /
410 MMU test added. simons 8352d 20h /
409 some minor changes to or1ksim; Testbench except.s modified. Interrupt test almost finished for uart ACV. markom 8353d 03h /
408 Fixed errant rx_bd_num erez 8353d 23h /
407 Initial revision. simons 8354d 00h /
406 Renamed ethernet's RX_BD_ADR to RX_BD_NUM erez 8354d 01h /
405 Stepping trough l.jal and l.jalr fixed. simons 8355d 03h /
404 is_delayed() is used outside this file. simons 8355d 03h /
403 Prompt changed because ddd requires (gdb). simons 8355d 03h /
402 Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32 lampret 8355d 07h /
401 *** empty log message *** simons 8358d 17h /
400 force_dslot_fetch does not work - allways zero. simons 8358d 17h /
399 Trap insn couses break after exits ex_insn. simons 8358d 17h /
398 added register field defines ivang 8360d 23h /
397 removed or16 architecture markom 8361d 00h /
396 added missing file markom 8361d 02h /
395 removed obsolete dependency and history from cpu section markom 8361d 04h /
394 dependency joined with dependstats; history moved to sim section markom 8361d 05h /
393 messages: exception on many places changed to abort markom 8361d 06h /
392 This commit was manufactured by cvs2svn to create tag 'stable'. 8361d 13h /
391 Fixed except_stop width and fixed EX PC for 1400444f no-ops. lampret 8361d 13h /
390 Changed instantiation name of VS RAMs. lampret 8361d 15h /
389 Changed default delay for load and store in superscalar cpu. lampret 8361d 15h /
388 Added comments for cpu section. lampret 8361d 15h /
387 Now FPGA and ASIC target are separate. lampret 8361d 17h /
386 Fixed VS RAM instantiation - again. lampret 8361d 17h /
385 check testbench now modified to work with new report output markom 8361d 23h /
384 modified simmem.cfg structure! ADD > BEFORE EACH LINE! markom 8362d 00h /
383 modified simmem.cfg structure! ADD markom 8362d 00h /
382 bitmask function bug fixed markom 8362d 02h /

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