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Rev Log message Author Age Path
991 Different memory controller. simons 7981d 20h /
990 Test is now complete. simons 7981d 20h /
989 c++ is making problems so, for now, it is excluded. simons 7983d 04h /
988 ORP architecture supported. simons 7983d 19h /
987 ORP architecture supported. simons 7984d 03h /
986 outputs out of function are not registered anymore markom 7984d 03h /
985 DTLB translation doesn't work on or1ksim when IC/DC enabled. lampret 7984d 15h /
984 Disable SB until it is tested lampret 7984d 15h /
983 First checkin lampret 7984d 17h /
982 Moved to sim/bin lampret 7984d 17h /
981 First checkin. lampret 7984d 17h /
980 Removed sim.tcl that shouldn't be here. lampret 7984d 17h /
979 Removed old test case binaries. lampret 7984d 17h /
978 Added variable delay for SRAM. lampret 7984d 17h /
977 Added store buffer. lampret 7984d 17h /
976 Added store buffer lampret 7984d 17h /
975 First checkin lampret 7984d 17h /
974 Enabled what works on or1ksim and disabled other tests. lampret 7984d 19h /
973 generated cuc top scheduler builds without syntax errors; not tested yet markom 7986d 23h /
972 Interrupt suorces fixed. simons 7987d 00h /
971 Now even keyboard test passes. simons 7987d 03h /
970 Testbench is now running on ORP architecture platform. simons 7987d 15h /
969 Checking in except directory. lampret 7988d 07h /
968 Checking in utils directory. lampret 7988d 07h /
967 Checking in mul directory. lampret 7988d 07h /
966 Checking in cbasic directory. lampret 7988d 07h /
965 Checking in basic directory. lampret 7988d 07h /
964 Checking in support directory. lampret 7988d 07h /
963 This commit was manufactured by cvs2svn to create tag 'rel_2'. 7988d 07h /
962 Fixed Xilinx trace buffer address. REported by Taylor Su. lampret 7988d 07h /

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