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Rev Log message Author Age Path
995 This commit was manufactured by cvs2svn to create tag 'rel_3'. 8051d 09h /
994 Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board. lampret 8051d 09h /
993 Fixed IMMU bug. lampret 8051d 09h /
992 A bug when cache enabled and bus error comes fixed. simons 8051d 18h /
991 Different memory controller. simons 8051d 18h /
990 Test is now complete. simons 8051d 19h /
989 c++ is making problems so, for now, it is excluded. simons 8053d 02h /
988 ORP architecture supported. simons 8053d 18h /
987 ORP architecture supported. simons 8054d 01h /
986 outputs out of function are not registered anymore markom 8054d 02h /
985 DTLB translation doesn't work on or1ksim when IC/DC enabled. lampret 8054d 13h /
984 Disable SB until it is tested lampret 8054d 14h /
983 First checkin lampret 8054d 16h /
982 Moved to sim/bin lampret 8054d 16h /
981 First checkin. lampret 8054d 16h /
980 Removed sim.tcl that shouldn't be here. lampret 8054d 16h /
979 Removed old test case binaries. lampret 8054d 16h /
978 Added variable delay for SRAM. lampret 8054d 16h /
977 Added store buffer. lampret 8054d 16h /
976 Added store buffer lampret 8054d 16h /
975 First checkin lampret 8054d 16h /
974 Enabled what works on or1ksim and disabled other tests. lampret 8054d 18h /
973 generated cuc top scheduler builds without syntax errors; not tested yet markom 8056d 22h /
972 Interrupt suorces fixed. simons 8056d 22h /
971 Now even keyboard test passes. simons 8057d 01h /
970 Testbench is now running on ORP architecture platform. simons 8057d 14h /
969 Checking in except directory. lampret 8058d 05h /
968 Checking in utils directory. lampret 8058d 05h /
967 Checking in mul directory. lampret 8058d 05h /
966 Checking in cbasic directory. lampret 8058d 05h /

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