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Rev	Log message	Author	Age	Path
114	This commit was manufactured by cvs2svn to create tag 'rel_7'.		7591d 10h	/
113	ifdefs moved to thier own lines, this confuses some of the tools.	simons	7591d 10h	/
112	This commit was manufactured by cvs2svn to create tag 'rel_6'.		7591d 15h	/
111	synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated.	simons	7591d 15h	/
110	Module that converts slave WISHBONE B3 accesses to WISHBONE B2 accesses with CAB.	mihad	7593d 14h	/
109	There was missing path to hdl.var file.	tadejm	7597d 12h	/
108	Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure.	tadejm	7597d 12h	/
107	Added status when checking disconnect with or without data. Before it was only retry, now there is stop and retry.	tadejm	7597d 12h	/
106	Added limited WISHBONE B3 support for WISHBONE Slave Unit. Doesn't support full speed bursts yet.	mihad	7602d 10h	/
105	Wrong pci_bridge32.v file included in the project!	mihad	7607d 17h	/
104	Found and simulated the problem in the synchronization logic. Repaired the synchronization logic in the FIFOs.	mihad	7607d 20h	/
103	Added test application and modified files to support it.	mihad	7654d 17h	/
102	Cleanup!	mihad	7654d 17h	/
101	Added simulation files.	mihad	7654d 17h	/
100	Cleanup!	mihad	7654d 17h	/
99	Cleanup!	mihad	7654d 18h	/
98	Cleanup.	mihad	7654d 18h	/
97	Doing a little bit of cleanup.	mihad	7654d 18h	/
96	Update!	mihad	7654d 18h	/
95	Removed this file, because it was too large - long download time.	mihad	7654d 18h	/
94	Changed one critical PCI bus signal logic.	mihad	7654d 18h	/
93	Added a test application!	mihad	7655d 01h	/
92	Update!	mihad	7655d 02h	/
91	WebPack 5.2 constraint file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de)	tadejm	7690d 16h	/
90	WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de)	tadejm	7690d 16h	/
89	Burst 2 error fixed.	mihad	7726d 16h	/
88	Added the reset value parameter to the synchronizer flop module. Added resets to all synchronizer flop instances. Repaired initial sync value in fifos.	mihad	7732d 15h	/
87	Updated acording to RTL changes.	mihad	7744d 13h	/
86	Entered the option to disable no response counter in wb master.	mihad	7744d 13h	/
85	Changed Vendor ID defines.	mihad	7744d 17h	/

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