OpenCores
URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] - Rev 119

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
119 Added support for WB B3. Some testcases were updated. tadejm 7604d 08h /
118 Some minor changes due to changes in core. tadejm 7604d 08h /
117 WB Master is now WISHBONE B3 compatible. tadejm 7604d 08h /
116 Corrected bug when writing to FIFO (now it is registered). tadejm 7604d 08h /
115 Added signals for WB Master B3. tadejm 7604d 08h /
114 This commit was manufactured by cvs2svn to create tag 'rel_7'. 7611d 11h /
113 ifdefs moved to thier own lines, this confuses some of the tools. simons 7611d 11h /
112 This commit was manufactured by cvs2svn to create tag 'rel_6'. 7611d 15h /
111 synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated. simons 7611d 15h /
110 Module that converts slave WISHBONE B3 accesses to
WISHBONE B2 accesses with CAB.		 mihad 7613d 15h /
109 There was missing path to hdl.var file. tadejm 7617d 12h /
108 Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure. tadejm 7617d 12h /
107 Added status when checking disconnect with or without data. Before it was only retry, now there is stop and retry. tadejm 7617d 12h /
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.		 mihad 7622d 10h /
105 Wrong pci_bridge32.v file included in the project! mihad 7627d 18h /
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.		 mihad 7627d 20h /
103 Added test application and modified files to support it. mihad 7674d 17h /
102 Cleanup! mihad 7674d 18h /
101 Added simulation files. mihad 7674d 18h /
100 Cleanup! mihad 7674d 18h /
99 Cleanup! mihad 7674d 18h /
98 Cleanup. mihad 7674d 18h /
97 Doing a little bit of cleanup. mihad 7674d 18h /
96 Update! mihad 7674d 18h /
95 Removed this file, because it was too large - long download time. mihad 7674d 18h /
94 Changed one critical PCI bus signal logic. mihad 7674d 18h /
93 Added a test application! mihad 7675d 02h /
92 Update! mihad 7675d 02h /
91 WebPack 5.2 constraint file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7710d 16h /
90 WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7710d 16h /

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.