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Rev	Log message	Author	Age	Path
81	Updated synchronization in top level fifo modules.	mihad	7808d 18h	/
80	This commit was manufactured by cvs2svn to create tag 'rel_4'.		7811d 23h	/
79	Updated.	mihad	7811d 23h	/
78	Old files with wrong names removed.	mihad	7811d 23h	/
77	Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.	mihad	7812d 00h	/
76	TRDY output delay was 10 instead of 11. Repaired.	mihad	7814d 23h	/
75	Include statement moved out of off/on pragma as reported by Uwe.	mihad	7818d 00h	/
74	This commit was manufactured by cvs2svn to create tag 'rel_3'.		7818d 00h	/
73	Bug fixes, testcases added.	mihad	7818d 00h	/
72	* empty log message *	mihad	7865d 04h	/
71	Changed the code a bit to make it more readable. Functionality not changed in any way. More robust synchronization in fifos is still pending.	mihad	7872d 20h	/
70	This commit was manufactured by cvs2svn to create tag 'rel_2'.		7910d 03h	/
69	Changed BIST signal names etc..	mihad	7910d 03h	/
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	7913d 13h	/
67	Changed BIST signals for RAMs.	tadejm	7913d 17h	/
66	Changed empty status generation in pciw_fifo_control.v	mihad	7917d 04h	/
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7920d 02h	/
64	The testcase I just added in previous revision repaired	mihad	7920d 04h	/
63	Added additional testcase and changed rst name in BIST to trst	mihad	7920d 06h	/
62	Added BIST signals for RAMs.	mihad	7922d 23h	/
61	This commit was manufactured by cvs2svn to create tag 'rel_1'.		7930d 23h	/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7930d 23h	/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7931d 00h	/
58	Removed all logic from asynchronous reset network	mihad	7936d 00h	/
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7936d 06h	/
56	Number of state bits define was removed	mihad	7936d 21h	/
55	Changed state machine encoding to true one-hot	mihad	7936d 22h	/
54	Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim	mihad	7969d 23h	/
53	Updated for synthesis purposes. Gate level simulation was failing in some configurations	mihad	7970d 03h	/
52	Oops, never before noticed that OC header is missing	mihad	7970d 07h	/

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[/] - Rev 81

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