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Rev	Log message	Author	Age	Path
82	This commit was manufactured by cvs2svn to create tag 'rel_5'.		7785d 17h	/
81	Updated synchronization in top level fifo modules.	mihad	7785d 17h	/
80	This commit was manufactured by cvs2svn to create tag 'rel_4'.		7788d 22h	/
79	Updated.	mihad	7788d 22h	/
78	Old files with wrong names removed.	mihad	7788d 23h	/
77	Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.	mihad	7788d 23h	/
76	TRDY output delay was 10 instead of 11. Repaired.	mihad	7791d 22h	/
75	Include statement moved out of off/on pragma as reported by Uwe.	mihad	7794d 23h	/
74	This commit was manufactured by cvs2svn to create tag 'rel_3'.		7794d 23h	/
73	Bug fixes, testcases added.	mihad	7794d 23h	/
72	* empty log message *	mihad	7842d 03h	/
71	Changed the code a bit to make it more readable. Functionality not changed in any way. More robust synchronization in fifos is still pending.	mihad	7849d 19h	/
70	This commit was manufactured by cvs2svn to create tag 'rel_2'.		7887d 02h	/
69	Changed BIST signal names etc..	mihad	7887d 02h	/
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	7890d 12h	/
67	Changed BIST signals for RAMs.	tadejm	7890d 17h	/
66	Changed empty status generation in pciw_fifo_control.v	mihad	7894d 03h	/
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7897d 01h	/
64	The testcase I just added in previous revision repaired	mihad	7897d 03h	/
63	Added additional testcase and changed rst name in BIST to trst	mihad	7897d 05h	/
62	Added BIST signals for RAMs.	mihad	7899d 22h	/
61	This commit was manufactured by cvs2svn to create tag 'rel_1'.		7907d 22h	/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7907d 22h	/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7907d 23h	/
58	Removed all logic from asynchronous reset network	mihad	7913d 00h	/
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7913d 06h	/
56	Number of state bits define was removed	mihad	7913d 20h	/
55	Changed state machine encoding to true one-hot	mihad	7913d 21h	/
54	Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim	mihad	7946d 23h	/
53	Updated for synthesis purposes. Gate level simulation was failing in some configurations	mihad	7947d 02h	/

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