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Rev	Log message	Author	Age	Path
87	Updated acording to RTL changes.	mihad	7775d 14h	/
86	Entered the option to disable no response counter in wb master.	mihad	7775d 14h	/
85	Changed Vendor ID defines.	mihad	7775d 18h	/
84	Changed vendor ID.	mihad	7779d 13h	/
83	Cleaned up the code. No functional changes.	mihad	7804d 11h	/
82	This commit was manufactured by cvs2svn to create tag 'rel_5'.		7818d 08h	/
81	Updated synchronization in top level fifo modules.	mihad	7818d 08h	/
80	This commit was manufactured by cvs2svn to create tag 'rel_4'.		7821d 13h	/
79	Updated.	mihad	7821d 13h	/
78	Old files with wrong names removed.	mihad	7821d 13h	/
77	Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.	mihad	7821d 13h	/
76	TRDY output delay was 10 instead of 11. Repaired.	mihad	7824d 12h	/
75	Include statement moved out of off/on pragma as reported by Uwe.	mihad	7827d 13h	/
74	This commit was manufactured by cvs2svn to create tag 'rel_3'.		7827d 13h	/
73	Bug fixes, testcases added.	mihad	7827d 13h	/
72	* empty log message *	mihad	7874d 17h	/
71	Changed the code a bit to make it more readable. Functionality not changed in any way. More robust synchronization in fifos is still pending.	mihad	7882d 09h	/
70	This commit was manufactured by cvs2svn to create tag 'rel_2'.		7919d 17h	/
69	Changed BIST signal names etc..	mihad	7919d 17h	/
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	7923d 02h	/
67	Changed BIST signals for RAMs.	tadejm	7923d 07h	/
66	Changed empty status generation in pciw_fifo_control.v	mihad	7926d 17h	/
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7929d 15h	/
64	The testcase I just added in previous revision repaired	mihad	7929d 18h	/
63	Added additional testcase and changed rst name in BIST to trst	mihad	7929d 19h	/
62	Added BIST signals for RAMs.	mihad	7932d 12h	/
61	This commit was manufactured by cvs2svn to create tag 'rel_1'.		7940d 12h	/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7940d 12h	/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7940d 14h	/
58	Removed all logic from asynchronous reset network	mihad	7945d 14h	/

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[/] - Rev 87

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