URL https://opencores.org/ocsvn/pit/pit/trunk

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Rev	Log message	Author	Age	Path
24	Added System Verilog Wishbone interface to module and testbench.	rehayes	4613d 07h	/
23	Simple language upgrade, will make bigger changes to add more system verilog features later.	rehayes	4698d 18h	/
22	Correct revision, compiles with VCS.	rehayes	4698d 18h	/
21	Simple language upgrade	rehayes	4699d 10h	/
20	minor update for timing constraint sugestions.	rehayes	5234d 12h	/
19	Minor change to add parameter to pit instance	rehayes	5234d 12h	/
18	Traded 16 data registers for 3 address registers when wait states are enabled.	rehayes	5234d 15h	/
17	Change WISHBONE ack signal so no output is generated when wait states are enabled and the bus transaction is terminated in the first cycle.	rehayes	5248d 11h	/
16	Added master error counter variable, added simulation timout limit	rehayes	5359d 14h	/
15	Fix blocking assigment	rehayes	5387d 15h	/
14	Cosmetic update, changed no-blocking assigment to blocking assigment	rehayes	5456d 13h	/
13	Update to rev 0.3, added SINGLE_CYCLE parameter	rehayes	5486d 16h	/
12	Fixed for single cycle reads	rehayes	5487d 12h	/
11	Changed read task to capture data at rising edge of clock	rehayes	5487d 12h	/
10	Added SINGLE_CYCLE parameter for WISHBONE bus cycles	rehayes	5488d 15h	/
9	fix problem with wb_wacc signal. Old method allowed data to be clocked into register twice.	rehayes	5494d 08h	/
8	Fix ack signal in testbench	rehayes	5494d 09h	/
7	Reflection of minor corrections	rehayes	5498d 14h	/
6	Reflection of minor corrections	rehayes	5498d 14h	/
5		rehayes	5536d 10h	/
4	Initial Release March 14, 2009 - Bob Hayes	rehayes	5536d 11h	/
3	Initial Release March 14, 2009 - Bob Hayes	rehayes	5536d 11h	/
2	Initial Release March 14, 2009 - Bob Hayes	rehayes	5536d 11h	/
1	The project was created and the structure was created	root	5537d 02h	/

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