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Rev	Log message	Author	Age	Path
47	Tag version 0.1 of the Potato Processor	skordal	3276d 10h	/
46	Remove branch: cache-playground	skordal	3279d 04h	/
45	Merge branch cache-playground (r23-r30 and r34-r44) into trunk This primarily adds the following features the the processor: - A direct-mapped instruction cache with configurable cache line width and number of cache lines. - Various bug fixes for bugs that appeared when the processor could run instructions at full speed but had to stall for data. - A "Hello World" test application.	skordal	3279d 04h	/
44	Add instruction cache and use the WB adapter as dmem interface	skordal	3279d 05h	/
43	Improve instruction fetch logic	skordal	3279d 05h	/
42	Move check for stall from irq_asserted to exception_taken in EX stage	skordal	3279d 05h	/
41	Make continouous status register reads asynchronous	skordal	3279d 05h	/
40	Reduce example design clock frequency to 50 MHz - Also includes a minor change to make the address decoder/interconnect work better with burst transfers.	skordal	3279d 05h	/
39	Disable IRQs when handling exceptions	skordal	3279d 05h	/
38	Add "Hello World" test application	skordal	3279d 06h	/
37	Add macro to set the TOHOST register from C code	skordal	3279d 06h	/
36	Ensure correct read of CSR after stall	skordal	3279d 06h	/
35	Prevent jumping/branching when stalling	skordal	3279d 06h	/
34	Prevent flushing the pipeline if it is stalling	skordal	3279d 06h	/
33	Ensure correct read of CSR after stall	skordal	3279d 06h	/
32	Prevent jumping/branching when stalling	skordal	3282d 04h	/
31	Prevent flushing the pipeline if it is stalling	skordal	3282d 05h	/
30	Add testcase for a combination of instructions that fail when using cache	skordal	3284d 09h	/
29	Add reset functionality for the WB arbiter state machine	skordal	3287d 04h	/
28	Add rudimentary User's manual	skordal	3293d 04h	/
27	Prevent exceptions from being taken while stalling	skordal	3293d 05h	/
26	Prevent exceptions from being taken while stalling Jumping to an exception handler while stalling and waiting for a load/store instruction to finish can cause undefined results from the load/store instruction. This actually fixes the issue mentioned in revision r20.	skordal	3293d 08h	/
25	Add placeholder cache modules and a wishbone arbiter	skordal	3295d 13h	/
24	Remove unused STRINGIFY macros	skordal	3296d 02h	/
23	Create branch to use for implementing a cache	skordal	3296d 02h	/
22	Fix the potato_get_badvaddr() macro	skordal	3296d 03h	/
21	Upgrade the example design to use a 60 MHz system clock	skordal	3296d 03h	/
20	Fix SHA256 benchmark crash by storing all registers on exception handler entry This problem will disappear when the processor is updated to conform to the new supervisor specification, which will allow us to use a compiler that conforms to the new "official" ABI.	skordal	3296d 03h	/
19	SHA256 benchmark: allow compiler to inline at will	skordal	3296d 03h	/
18	instr_misalign_check: add do_jump to sensitivity list	skordal	3298d 03h	/

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