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Rev Log message Author Age Path
27 added 8-bit access to divider register. gorand 7578d 03h /
26 This commit was manufactured by cvs2svn to create tag 'rel_6'. 7612d 10h /
25 unit delay on registers added primozs 7612d 10h /
24 support for configurable devider added primozs 7612d 12h /
23 Added an option to use constant values instead of RAM
in the translation table.		 mihad 7706d 09h /
22 This commit was manufactured by cvs2svn to create tag 'rel_5'. 7707d 07h /
21 Error fixed again. simons 7707d 07h /
20 This commit was manufactured by cvs2svn to create tag 'rel_4'. 7707d 07h /
19 Error fixed. simons 7707d 07h /
18 This commit was manufactured by cvs2svn to create tag 'rel_3'. 7735d 05h /
17 resetall keyword removed. ifdef moved to a separated line. simons 7735d 05h /
16 This commit was manufactured by cvs2svn to create tag 'rel_2'. 7740d 06h /
15 Change the address width. simons 7740d 06h /
14 This commit was manufactured by cvs2svn to create tag 'rel_1'. 8154d 09h /
13 Added mouse interface and everything for its handling, cleaned up some unused code mihad 8154d 09h /
12 Mouse interface testcases added mihad 8154d 09h /
11 Mouse interface added mihad 8154d 09h /
10 Wrong acknowledge generation during receiving repaired mihad 8154d 09h /
9 Added one more ps2 state machine for mouse interface mihad 8154d 09h /
8 Updated ucf with wildcards to make it more independant mihad 8201d 08h /
7 Little/big endian changes continued mihad 8202d 05h /
6 Little/big endian changes incorporated mihad 8202d 07h /
5 One bug fixed mihad 8204d 04h /
4 Changed defines for simulation to work without xilinx primitives mihad 8204d 05h /
3 This commit was manufactured by cvs2svn to create tag 'GATE_LEVEL_SIM_OK'. 8204d 06h /
2 Initial project import - working mihad 8204d 06h /
1 Standard project directories initialized by cvs2svn. 8204d 06h /

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