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Rev	Log message	Author	Age	Path
24	New directory structure.	root	5581d 21h	/
23	- when freeze or stall; don't let memory operations - Modification on the CP0 - The CP0 is deplaced in the WB stage - The INT, SI event signals are treated asynchronously in the WB stage - The rCAUSE register is asynchronous now - The wException signal is asyncronous instantanously - Add a repeat/continous treatement (not completed yet) - *** The "INT EXCEPTION NO STALL" work correctly	ameziti	5940d 07h	/
22	- Some modifications for testing exception.	ameziti	5974d 23h	/
21	- Flush must be on all signals in the pipeline.	ameziti	5974d 23h	/
20	- Modification of CP0 to wait the end of all stalls before to process Exception. - Set "Exception sign" active until all Stalls are completed.	ameziti	5975d 07h	/
19	- Exception signals must be stalled, flushed, stoped or cleared(except reset) - Look at 14-07-2007 - except the asynchronous event like "external interruption"	ameziti	5975d 13h	/
18	- Read/Write of the CP0 register is in the WB stage, but Exception detection begin from the MEM stage.	ameziti	5975d 13h	/
17	- UnFonctional Modifications: Change the name of the address port of "CP0".	ameziti	5975d 14h	/
16	- Remove All generable files from the project.	ameziti	5975d 21h	/
15	- UnFonctional Modifications. - Change the "CP0" define to "EXCEPTION".	ameziti	5975d 22h	/
14	Remove unnecessary files from project.	ameziti	5976d 06h	/
13	- To simplify the exception traitement: Instruction are executed serialy. - Exception event must be treated CONCURRENTLY with the other event that stall the pipeline.	ameziti	5976d 06h	/
12	To simplify the exception traitement: Instruction are executed serialy.	ameziti	5976d 07h	/
11	Exception event must be treated CONCURRENTLY with the other event that stall the pipeline.	ameziti	5976d 07h	/
10	Modification of the CP0.	ameziti	5976d 08h	/
9	When D-Cache miss, there's no need to stall MEMWB and freeze WB. The solution is to flush MEMWB only.	ameziti	5976d 08h	/
8	Enhancement of the "Controler specification doc".	ameziti	5979d 08h	/
7	Add Pipeline Controler specification documentation.	ameziti	5980d 06h	/
6	When D-Cache miss, there's no need to stall MEMWB and freeze WB. The solution is to flush MEMWB only.	ameziti	5980d 08h	/
5	Remove the Multiple Arithmetic Unit fonction. - The Pipeline must stall when Mult/Div unit is busy. - Whether there's a mflo or mfhi. - see `define MULTIPLE_ALU	ameziti	5981d 06h	/
4	Add Soc Image in the Specification documentation	ameziti	6002d 08h	/
3	This commit was manufactured by cvs2svn to create tag 'arelease'.		6003d 17h	/
2	First Import the project on the opencores.org CVS server	ameziti	6003d 17h	/
1	Standard project directories initialized by cvs2svn.		6003d 17h	/

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Subversion Repositories r2000

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