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URL https://opencores.org/ocsvn/r2000/r2000/trunk

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32 b ameziti 5410d 14h /
31 a ameziti 5410d 14h /
30 ameziti 5425d 15h /
29 ameziti 5425d 15h /
28 ameziti 5426d 01h /
27 The design doesn't work correctly. ameziti 5426d 01h /
26 Added old uploaded documents to new repository. root 5562d 09h /
25 Added old uploaded documents to new repository. root 5562d 15h /
24 New directory structure. root 5562d 15h /
23 - when freeze or stall; don't let memory operations
- Modification on the CP0
- The CP0 is deplaced in the WB stage
- The INT, SI event signals are treated asynchronously in the WB stage
- The rCAUSE register is asynchronous now
- The wException signal is asyncronous instantanously
- Add a repeat/continous treatement (not completed yet)

- *** The "INT EXCEPTION NO STALL" work correctly		 ameziti 5921d 01h /
22 - Some modifications for testing exception. ameziti 5955d 17h /
21 - Flush must be on all signals in the pipeline. ameziti 5955d 17h /
20 - Modification of CP0 to wait the end of all stalls before to process Exception.
- Set "Exception sign" active until all Stalls are completed.		 ameziti 5956d 00h /
19 - Exception signals must be stalled, flushed, stoped or cleared(except reset)
- Look at 14-07-2007
- except the asynchronous event like "external interruption"		 ameziti 5956d 07h /
18 - Read/Write of the CP0 register is in the WB stage, but Exception detection begin from the MEM stage. ameziti 5956d 07h /
17 - UnFonctional Modifications: Change the name of the address port of "CP0". ameziti 5956d 07h /
16 - Remove All generable files from the project. ameziti 5956d 15h /
15 - UnFonctional Modifications.
- Change the "CP0" define to "EXCEPTION".		 ameziti 5956d 16h /
14 Remove unnecessary files from project. ameziti 5957d 00h /
13 - To simplify the exception traitement: Instruction are executed serialy.
- Exception event must be treated CONCURRENTLY with the other event that stall the pipeline.		 ameziti 5957d 00h /
12 To simplify the exception traitement: Instruction are executed serialy. ameziti 5957d 01h /
11 Exception event must be treated CONCURRENTLY with the other event that stall the pipeline. ameziti 5957d 01h /
10 Modification of the CP0. ameziti 5957d 01h /
9 When D-Cache miss, there's no need to stall MEMWB and freeze WB.
The solution is to flush MEMWB only.		 ameziti 5957d 01h /
8 Enhancement of the "Controler specification doc". ameziti 5960d 01h /
7 Add Pipeline Controler specification documentation. ameziti 5961d 00h /
6 When D-Cache miss, there's no need to stall MEMWB and freeze WB.
The solution is to flush MEMWB only.		 ameziti 5961d 02h /
5 Remove the Multiple Arithmetic Unit fonction.
- The Pipeline must stall when Mult/Div unit is busy.
- Whether there's a mflo or mfhi.
- see `define MULTIPLE_ALU		 ameziti 5961d 23h /
4 Add Soc Image in the Specification documentation ameziti 5983d 02h /
3 This commit was manufactured by cvs2svn to create tag 'arelease'. 5984d 10h /

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