| Rev |
Log message |
Author |
Age |
Path |
| 242 |
AS1 produced an unnoticed delay, the compiler geenerated an extra stage..... so a delay constant was added to sync this extra stage with the operation via ssync_chain |
jguarin2002 |
4347d 02h |
/ |
| 241 |
fmul32 x 6 multipliers wide |
jguarin2002 |
4347d 23h |
/ |
| 240 |
last minute correction |
jguarin2002 |
4348d 03h |
/ |
| 239 |
wide multiplicator added to avoid optimization |
jguarin2002 |
4348d 03h |
/ |
| 238 |
wide multiplicator added to avoid optimization |
jguarin2002 |
4348d 03h |
/ |
| 237 |
corrected errors in raytrac.vhd |
jguarin2002 |
4348d 05h |
/ |
| 236 |
Tunnning delay added to q0 queue |
jguarin2002 |
4348d 08h |
/ |
| 235 |
Tunnning delay added to q0 queue |
jguarin2002 |
4348d 08h |
/ |
| 234 |
raytrac update nothing major |
jguarin2002 |
4349d 08h |
/ |
| 233 |
raytrac sopc component updated |
jguarin2002 |
4349d 08h |
/ |
| 232 |
raytrac sopc component updated |
jguarin2002 |
4349d 08h |
/ |
| 231 |
nfetch address counter implemented in a whole register for convinience |
jguarin2002 |
4349d 09h |
/ |
| 230 |
RC 1.0 Previous rev(228), is functional and even more than this one, but is bigger and is for debugging |
jguarin2002 |
4354d 11h |
/ |
| 229 |
Total RtEngine Hardware, BUT, problems with interconnection... perhaps theres a problem with long path on ssumando5 |
jguarin2002 |
4355d 11h |
/ |
| 228 |
Fixed a BUG where big differences betweeen exponents difference suffered from miss-signedness because of the width of the result was 1 bit narrower, and still its highest significant bit was taken as the sign, in result big differences in where taken as negative results... leading to situations like A+0=0 cause the exponent chosen as the big one was the zero's (-127) leading to an unexpected 0 in the result. The bug was fixed by correcting the signedness of the operation and making the result less narrower in one bit. |
jguarin2002 |
4357d 04h |
/ |
| 227 |
Fixed a BUG where big differences betweeen exponents difference suffered from miss-signedness because of the width of the result was 1 bit narrower, and still its highest significant bit was taken as the sign, in result big differences in where taken as negative results... leading to situations like A+0=0 cause the exponent chosen as the big one was the zero's (-127) leading to an unexpected 0 in the result. The bug was fixed by correcting the signedness of the operation and making the result less narrower in one bit. |
jguarin2002 |
4357d 08h |
/ |
| 226 |
Documento 90%, falta el glosario de siglas, el anexo de referencia de RTLs, el capitulo 9 (trazador de rayos) y la bibiliografia |
jguarin2002 |
4357d 09h |
/ |
| 225 |
Documento 90%, falta el glosario de siglas, el anexo de referencia de RTLs, el capitulo 9 (trazador de rayos) y la bibiliografia |
jguarin2002 |
4357d 09h |
/ |
| 224 |
Documento 90%, falta el glosario de siglas, el anexo de referencia de RTLs, el capitulo 9 (trazador de rayos) y la bibiliografia |
jguarin2002 |
4357d 10h |
/ |
| 223 |
Reportes para NS_JULI_SDF_ASM_AP_DMA_130812_21028 |
jguarin2002 |
4364d 08h |
/ |
| 222 |
documento en un 55\% |
jguarin2002 |
4364d 09h |
/ |
| 221 |
The change in sqrt and inv is about the path of the files with the data memory. dpc has been changed by ap_n_dpc and there was an error on RayTrac related to the load sync chain: the loading of Dot product Operation was being carried out as if it was an unary operation rather than a two operands operation |
jguarin2002 |
4366d 18h |
/ |
| 220 |
ap_n_dpc.vhd es el RTL que integra DataPathControl y ArithPipeLine |
jguarin2002 |
4366d 19h |
/ |
| 219 |
RayTrac: Non tested and witouh TSE |
jguarin2002 |
4366d 21h |
/ |
| 218 |
Raytrac : NS_JULI_DSF_ASM_DMA_120812_18081 : SOPC Library TCL scrip, load it into the Altera Project |
jguarin2002 |
4367d 01h |
/ |
| 217 |
Raytrac : NS_JULI_DSF_ASM_DMA_120812_18081 : \n+ NIOS 2 Standard\n+ JTAG UART | UART | LCD | I2C TOUCH SCREEN\n+ DDR SDRAM | SSRAM | FLASH \n+ Avalon Memory Mapped Master Interface | Avalon Memory Mapped Slave Interface \n+ Direct Memory Access Support \n+ 18081 logic elements out of 24624 (73%) used |
jguarin2002 |
4367d 01h |
/ |
| 216 |
At the moment memblock.vhd described 3 things: an input params queue (discarded, input control is made with master_readdatavalid signal and load_sync_chain) a load sync_chain(implemented in raytrac.vhd) and 4 result queues, which were implemented as a single result queue in raytrac.vhd).\n\n\ncustom_counter and Raytrac_control, are no longer needed |
jguarin2002 |
4367d 16h |
/ |
| 215 |
At the moment memblock.vhd described 3 things: an input params queue (discarded, input control is made with master_readdatavalid signal and load_sync_chain) a load sync_chain(implemented in raytrac.vhd) and 4 result queues, which were implemented as a single result queue in raytrac.vhd).\n\n\ncustom_counter and Raytrac_control, are no longer needed |
jguarin2002 |
4367d 16h |
/ |
| 214 |
At the moment memblock.vhd described 3 things: an input params queue (discarded, input control is made with master_readdatavalid signal and load_sync_chain) a load sync_chain(implemented in raytrac.vhd) and 4 result queues, which were implemented as a single result queue in raytrac.vhd).\n\n\ncustom_counter and Raytrac_control, are no longer needed |
jguarin2002 |
4367d 16h |
/ |
| 213 |
Arithpack: changes to suppport the Beta Raytrac RTL description (with almost DMA caps) |
jguarin2002 |
4367d 16h |
/ |
