URL https://opencores.org/ocsvn/raytrac/raytrac/trunk

Subversion Repositories raytrac

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Rev	Log message	Author	Age	Path
59	Tarde con pintiti, paquete aritmetico se anade raiz shifter y sqrt	jguarin2002	4828d 23h	/
58	Testbenching corrections.....	jguarin2002	4838d 19h	/
57	testbench verification AWFUL HORRIBLE BAD WRITTEN GREMLIN PROGRAM	jguarin2002	4839d 18h	/
56	Stop conditions.....	jguarin2002	4846d 23h	/
55	Unifying Testbench written files format......	jguarin2002	4847d 00h	/
54	Unifying Testbench written files format......	jguarin2002	4847d 02h	/
53	Improved TRACE_rom_contents.csv presentation	jguarin2002	4854d 11h	/
52	Working......	jguarin2002	4875d 10h	/
51	There's now a descent testbench 2.0\!\!\!	jguarin2002	4882d 10h	/
50	There's now a descent testbench\!\!\!	jguarin2002	4883d 15h	/
49	Test bench ifs finally running	jguarin2002	4884d 10h	/
48	Developing first testbench.... also learning how to do it	jguarin2002	4886d 07h	/
47	Started making tests, but dont understand quite well the mechanics of Modelsim. Change Arithpack for quicker multiplier and memory instantiation	jguarin2002	4887d 18h	/
46	simplified memory path	jguarin2002	4887d 21h	/
45	Magic is already written... now we shall set the testbench on fire\!	jguarin2002	4889d 09h	/
44	All components in the test bench are now instantiated what is left now is the magic, menaing the test algorithm... also rom memories with crash test dummies are addedsvn add memax.mif memay.mif memaz.mif membx.mif memby.mif membz.mif memcx.mif memcy.mif memcz.mif memdx.mif memdy.mif memdz.mifsvn add memax.mif memay.mif memaz.mif membx.mif memby.mif membz.mif memcx.mif memcy.mif memcz.mif memdx.mif memdy.mif memdz.mif...	jguarin2002	4890d 10h	/
43	Nothing to say, just working on the Test Bench...	jguarin2002	4890d 18h	/
42	no comment no tb yet:	jguarin2002	4891d 11h	/
41	Ram for the massses\!\!\!	jguarin2002	4893d 22h	/
40	test bench changes.....	jguarin2002	4893d 22h	/
39	Perhaps its a good idea to have a todo.txt file under version control	jguarin2002	4895d 19h	/
38	Tb ggodies	jguarin2002	4897d 10h	/
37	Testbenchgoodies	jguarin2002	4897d 10h	/
36	testbench for rtengine test	jguarin2002	4897d 21h	/
35	oops stderr -> stdout, fixed	jguarin2002	4897d 21h	/
34	No need for .h	jguarin2002	4897d 23h	/
33	Program to create a MIF (memory initialization file) in order to simulate RtEngine	jguarin2002	4901d 09h	/
32	carry_logic parameter added to uf entity	jguarin2002	4904d 01h	/
31	enable signal retaken, and error corrected, a really big mistake	jguarin2002	4904d 09h	/
30	enable signal retaken... ooops a little lapsus	jguarin2002	4904d 09h	/

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[/] - Rev 59

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