URL https://opencores.org/ocsvn/rio/rio/trunk

Subversion Repositories rio

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Rev	Log message	Author	Age	Path
30	Changing name tags/1.0.1 to tags/1.0.1-release.	magro732	3584d 18h	/
29	Fixed bug in RioSwitch internal Wishbone interconnects.	magro732	3584d 19h	/
28	Correcting bug in RioSwitch.vhd internal Wishbone interconnect. Modifying an existing test case in TestRioSwitch.vhd to provoke the error.	magro732	3584d 19h	/
27	Adding missing code to single-symbol pipelined transmitter. Not tested nor copiled.	magro732	3586d 07h	/
26	Temporary checkin of parallelSymbols branch. It does not work yet.	magro732	3746d 18h	/
25	Correcting compiler errors in TestRioPcsUart.vhd	magro732	3753d 12h	/
24	Changing errornous use statement.	magro732	3753d 12h	/
23	Tagging alpha release 2.0.0.	magro732	3870d 06h	/
22	Tagging release 1.0.0.	magro732	3870d 06h	/
21	Branching of a single symbol version of the new RioSerial.	magro732	3870d 06h	/
20	Adding software C-stack and matching VHDL modules.	magro732	3935d 09h	/
19	Removing synthesis warnings.	magro732	3960d 08h	/
18	Making RioSerial entity the same as before+minor fixes.	magro732	3961d 07h	/
17	Removing latch and improving timing.	magro732	3962d 07h	/
16	Removed FIFO between RioSerial and PCS. Transmitter works without idle ticks. Internal symbol fifo increased. Changed readContentEnd_o timing.	magro732	3962d 08h	/
15	All testcases are ok. Still needs some tweeks though.	magro732	3966d 09h	/
14	Most issues solved, testbench issues remains.	magro732	3969d 08h	/
13	Timeouts are working.	magro732	3972d 09h	/
12	Backup of recent work, debugging new RioSerial.	magro732	3983d 07h	/
11	Receiver ready, transmitter is compiling.	magro732	3983d 08h	/
10	Branch to develop support for parallel symbols.	magro732	3983d 08h	/
9	Adding the recently written PCS code, which connects the RioSerial to the Virtex-6 GTX-Quad (4-Lane SerDes)	azdem	4024d 20h	/
8	Adding signal descriptions in comments.	magro732	4068d 09h	/
7	Adding missing generic parameters to RioPacketBuffer.	magro732	4155d 13h	/
6	Adding RioWbBridge. Sorry, no testbench for this one.	magro732	4155d 15h	/
5	Uploading primitive documentation.	magro732	4162d 07h	/
4	Adding protocol engine implementing the hardware independent parts of the LP-serial physical specification.	magro732	4184d 20h	/
3	Adding RioPacketBuffer and testbench.	magro732	4185d 12h	/
2	Adding RioSwitch and testbench.	magro732	4185d 14h	/
1	The project and the structure was created	root	4186d 20h	/

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