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URL https://opencores.org/ocsvn/rise/rise/trunk

Subversion Repositories rise

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Rev Log message Author Age Path
151 Started to include generic VHDL description of memories. jlechner 5240d 15h /
150 Added old uploaded documents to new repository. root 5576d 20h /
149 Added old uploaded documents to new repository. root 5577d 02h /
148 New directory structure. root 5577d 02h /
147 - Updated to use current example. cwalter 6351d 10h /
146 - Changed to compile UART example. cwalter 6351d 12h /
145 - Added more VHDL files to project. cwalter 6351d 12h /
144 - IF stage now uses autogenerated VHDL files. cwalter 6351d 12h /
143 - Added more complex UART example. cwalter 6351d 13h /
142 - Added gap between characters sent and changed last character to CR. cwalter 6351d 13h /
141 - Added delay between characters. cwalter 6351d 13h /
140 - Test bench for RISE with UART. cwalter 6351d 13h /
139 - Added makefile example to improve design flow.
- Added subroutine example.		 cwalter 6351d 14h /
138 - Fixed binary to VHDL converter. cwalter 6351d 14h /
137 - Added binary to VHDL converter. cwalter 6351d 15h /
136 - Added makefile example to improve design flow.
- Added subroutine example.		 cwalter 6351d 15h /
135 uart_address_0 was a latch -> changed ustadler 6352d 11h /
134 Added second test program for testing uart. jlechner 6352d 11h /
133 - Fixed bug with ST opcodes. cwalter 6352d 13h /
132 Added test program for testing uart. jlechner 6352d 13h /
131 Changed high active resets to low active ones. jlechner 6352d 13h /
130 Removed obsolete line jlechner 6352d 13h /
129 Sample assembler program for accessing uart jlechner 6352d 13h /
128 Added multiplexer for output data. This mutliplexer decides on the adress of the last cycles
if ordinary memory data or data of an extension module have to be passed on.		 jlechner 6352d 13h /
127 Changed high active resets to low active ones. jlechner 6352d 13h /
126 Added constant for cpu frequency (needed for UART) trinklhar 6352d 20h /
125 Fixed vhdl bugs trinklhar 6352d 20h /
124 Assigned UART signals to ports on top-level entity trinklhar 6352d 20h /
123 Removed UART again trinklhar 6352d 21h /
122 Removed UART again again trinklhar 6352d 21h /

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