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Subversion Repositories rise

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Rev Log message Author Age Path
151 Started to include generic VHDL description of memories. jlechner 5249d 09h /
150 Added old uploaded documents to new repository. root 5585d 14h /
149 Added old uploaded documents to new repository. root 5585d 21h /
148 New directory structure. root 5585d 21h /
147 - Updated to use current example. cwalter 6360d 05h /
146 - Changed to compile UART example. cwalter 6360d 07h /
145 - Added more VHDL files to project. cwalter 6360d 07h /
144 - IF stage now uses autogenerated VHDL files. cwalter 6360d 07h /
143 - Added more complex UART example. cwalter 6360d 07h /
142 - Added gap between characters sent and changed last character to CR. cwalter 6360d 07h /
141 - Added delay between characters. cwalter 6360d 07h /
140 - Test bench for RISE with UART. cwalter 6360d 08h /
139 - Added makefile example to improve design flow.
- Added subroutine example.		 cwalter 6360d 08h /
138 - Fixed binary to VHDL converter. cwalter 6360d 08h /
137 - Added binary to VHDL converter. cwalter 6360d 09h /
136 - Added makefile example to improve design flow.
- Added subroutine example.		 cwalter 6360d 09h /
135 uart_address_0 was a latch -> changed ustadler 6361d 05h /
134 Added second test program for testing uart. jlechner 6361d 05h /
133 - Fixed bug with ST opcodes. cwalter 6361d 07h /
132 Added test program for testing uart. jlechner 6361d 07h /
131 Changed high active resets to low active ones. jlechner 6361d 07h /
130 Removed obsolete line jlechner 6361d 07h /
129 Sample assembler program for accessing uart jlechner 6361d 07h /
128 Added multiplexer for output data. This mutliplexer decides on the adress of the last cycles
if ordinary memory data or data of an extension module have to be passed on.		 jlechner 6361d 08h /
127 Changed high active resets to low active ones. jlechner 6361d 08h /
126 Added constant for cpu frequency (needed for UART) trinklhar 6361d 14h /
125 Fixed vhdl bugs trinklhar 6361d 14h /
124 Assigned UART signals to ports on top-level entity trinklhar 6361d 14h /
123 Removed UART again trinklhar 6361d 15h /
122 Removed UART again again trinklhar 6361d 15h /

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