URL https://opencores.org/ocsvn/rise/rise/trunk

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[/] - Rev 89

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Rev	Log message	Author	Age	Path
89	Added input signal for clearing all register locks.	jlechner	6411d 21h	/
88	- Added new patch for assembler.	cwalter	6411d 21h	/
87	no message	cwalter	6411d 21h	/
86	- Added new example for a more complex loop.	cwalter	6411d 21h	/
85	Removed PC reset on clear_in signal. Clear_in only comes together with a branch, so it is sufficient branch immediately.	jlechner	6412d 00h	/
84	- PC value was wrong.	cwalter	6412d 00h	/
83	- sr_enable and lr_enable where incorrect.	cwalter	6412d 00h	/
82	- Updated drawings for memory.	cwalter	6412d 00h	/
81	- Changed to include barrel shifter.	cwalter	6412d 00h	/
80	- Fixed testbench to work with new barrel shifter.	cwalter	6412d 00h	/
79	- Added barrel shifter.	cwalter	6412d 00h	/
78	Added stall_in to sensitivity list.	jlechner	6412d 00h	/
77	- Fixed case.	cwalter	6412d 00h	/
76	- Changed order of some statements to improve readability.	cwalter	6412d 00h	/
75	- Added barrel shifter implementation.	cwalter	6412d 00h	/
74	- Fixed bug where register value used by load was passed through to write back. Correct is ALU value.	cwalter	6412d 02h	/
73	- Fixed bug where immediate value for LD_IMM_HB was placed in the upper 8bits. This is done by the execute stage.	cwalter	6412d 02h	/
72	Added RISE_PACK_SPECIFIC containing either - constants declarations for synthesis or - enumeration types for simulation Added call to conversion function where a std_logic_vector is assigned to a opcode signal or a condition signal.	jlechner	6412d 11h	/
71	Added RISE_PACK_SPECIFIC containing either - constants declarations for synthesis or - enumeration types for simulation	jlechner	6412d 11h	/
70	Moved opcode and conditional constants and opcode_t and cond_t data types to rise_const_pack.vhd.	jlechner	6412d 11h	/
69	Synthesis package containing opcode and conditional constants used in other vhd files. Package also contains convert functions from std_logic_vector to the appropriate data type.	jlechner	6412d 11h	/
68	Simulation package containing enumeration types for opcodes and condition codes. Package also contains convert functions from std_logic_vector to the appropriate enumeration type.	jlechner	6412d 11h	/
67	- Added assembler file.	cwalter	6412d 12h	/
66	Moved constants for opcode and conditionals in seperate package.	jlechner	6412d 12h	/
65	Added correct register signals	jlechner	6412d 12h	/
64	* empty log message *	jlechner	6412d 12h	/
63	- Added missing signal stall_out_int to sensitivity list. - LR register now locked if opcode is JUMP.	cwalter	6412d 13h	/
62	no message	cwalter	6412d 15h	/
61	- Applied indenting tool. - Added first basic implementation for testing.	cwalter	6412d 15h	/
60	- Applied indenting tool.	cwalter	6412d 15h	/

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[/] - Rev 89

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