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Rev	Log message	Author	Age	Path
66	Modified to use XG syntax	fafa1971	6101d 18h	/
65	Version with undisclosed library names	fafa1971	6101d 18h	/
64	Initial version B C C Initial versioNCVS: ----------------------------------------------------------------------	fafa1971	6101d 18h	/
63	* empty log message *	fafa1971	6101d 18h	/
62	Documentation files updated to reflect the 3 different flavors of S1 Core	fafa1971	6147d 16h	/
61	Updated to latest version	fafa1971	6147d 17h	/
60	Now supports also Virtex5 devices	fafa1971	6147d 17h	/
59	Now it is just one line	fafa1971	6147d 17h	/
58	These were only symbolic links to remember where such these things were defined	fafa1971	6147d 17h	/
57	Latest version	fafa1971	6147d 17h	/
56	Updated from OpenSPARC T1 version 1.4 to version 1.5	fafa1971	6147d 17h	/
55	Nobody remembers why these blackboxed files were required!	fafa1971	6147d 17h	/
54	Updated filelists	fafa1971	6147d 17h	/
53	Removed from CVS tree because header file preprocessing is done elsewhere	fafa1971	6147d 17h	/
52	Updated SPARC Core files from OpenSPARC T1 version 1.4 to version 1.5	fafa1971	6147d 17h	/
51	User Chris "gaterocket" corrected a couple of errors for FPGA boards: blocking assignments and two uninitialized variables.	fafa1971	6233d 17h	/
50	Changed library paths for XST from macrocell to behav.	fafa1971	6250d 00h	/
49	Now supports 3 versions: S1 Core ME/SE/EE.	fafa1971	6257d 01h	/
48	Updated with new OpenSPARC 1.4 list	fafa1971	6298d 16h	/
47	Updated with `define preprocessing for Xilinx XST synthesis	fafa1971	6298d 16h	/
46	Fresh version from OpenSPARC 1.4 and Icarus define preprocessing	fafa1971	6298d 16h	/
45	I'm going to remove original OpenSPARC 1.4 files so that I can insert again the ones with Icarus Verilog preprocessor already applied by update_sparccore (it seems that Xilinx's XST does NOT support defines at compile time)	fafa1971	6298d 16h	/
44	Embedded `defines into Verilog source since did not find command line option for XST	fafa1971	6299d 14h	/
43	Added welcome message as a remainder to set paths for tools!=IVerilog	fafa1971	6299d 14h	/
42	Added support for filelist for Xilinx ISE XST synthesis	fafa1971	6299d 14h	/
41	Added copy of empty modules upon original SPARC copies	fafa1971	6299d 14h	/
40	First version of synthesis script for Xilinx ISE XST	fafa1971	6299d 14h	/
39	Empty modules for cacheless Simply RISC S1 Core	fafa1971	6299d 14h	/
38	Changed to compile (for now) the boot code.	fafa1971	6303d 13h	/
37	Memory image coming from the new boot.s	fafa1971	6303d 13h	/

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