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Rev Log message Author Age Path
64 CAS Latency support added for 4,5 dinesha 4363d 12h /
63 FPGA Bench mark results are added dinesha 4482d 11h /
62 Synthesis constraint for simplify dinesha 4482d 11h /
61 RTL file list are added into SVN dinesha 4482d 12h /
60 warning cleanup dinesha 4482d 12h /
59 Control path request and data are register now for better FPGA timing dinesha 4482d 12h /
58 Read Data is register on RD_FAST=0 case dinesha 4482d 12h /
57 Synthesis constraints are added dinesha 4483d 03h /
56 FPGA Synth optimisation dinesha 4483d 04h /
55 FPGA Synthesis timing optimisation dinesha 4483d 04h /
54 FPGA Timing Optimisation dinesha 4486d 02h /
53 Test bench upgradation dinesha 4487d 02h /
52 Documentation update for request control and transfer control block dinesha 4487d 02h /
51 FPGA relating timing optimisation done dinesha 4487d 02h /
50 Bug fix the request length is fixe dinesha 4489d 06h /
49 clean up dinesha 4490d 05h /
48 top-level cleanup dinesha 4490d 05h /
47 SDRAM bus converter bug fix and top-level signal clean up dinesha 4490d 05h /
46 test bench upgrade + rtl cleanup dinesha 4492d 06h /
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4492d 10h /
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4494d 08h /
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 4494d 10h /
42 Bug fix in read access is fixed dinesha 4494d 10h /
41 Updated Spec ver 0.1 is added back to svn dinesha 4494d 12h /
40 Application layer Fifo full conditional are register now to synth timing fixes dinesha 4495d 05h /
39 Test Bench upgradation with bigger data burst size dinesha 4495d 05h /
38 Port Name clean up dinesha 4496d 10h /
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4496d 12h /
36 Clean up dinesha 4497d 03h /
35 Updated the New Documents - ver 0.1 dinesha 4497d 04h /

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