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Rev Log message Author Age Path
66 dwm tw, bl paramter are passed on the wb2sdrc module dinesha 4389d 10h /
65 Updated Log file with CAS latency support 4,5 dinesha 4389d 18h /
64 CAS Latency support added for 4,5 dinesha 4389d 18h /
63 FPGA Bench mark results are added dinesha 4508d 17h /
62 Synthesis constraint for simplify dinesha 4508d 17h /
61 RTL file list are added into SVN dinesha 4508d 17h /
60 warning cleanup dinesha 4508d 18h /
59 Control path request and data are register now for better FPGA timing dinesha 4508d 18h /
58 Read Data is register on RD_FAST=0 case dinesha 4508d 18h /
57 Synthesis constraints are added dinesha 4509d 08h /
56 FPGA Synth optimisation dinesha 4509d 09h /
55 FPGA Synthesis timing optimisation dinesha 4509d 09h /
54 FPGA Timing Optimisation dinesha 4512d 07h /
53 Test bench upgradation dinesha 4513d 07h /
52 Documentation update for request control and transfer control block dinesha 4513d 08h /
51 FPGA relating timing optimisation done dinesha 4513d 08h /
50 Bug fix the request length is fixe dinesha 4515d 12h /
49 clean up dinesha 4516d 11h /
48 top-level cleanup dinesha 4516d 11h /
47 SDRAM bus converter bug fix and top-level signal clean up dinesha 4516d 11h /
46 test bench upgrade + rtl cleanup dinesha 4518d 12h /
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4518d 16h /
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4520d 14h /
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 4520d 16h /
42 Bug fix in read access is fixed dinesha 4520d 16h /
41 Updated Spec ver 0.1 is added back to svn dinesha 4520d 17h /
40 Application layer Fifo full conditional are register now to synth timing fixes dinesha 4521d 10h /
39 Test Bench upgradation with bigger data burst size dinesha 4521d 10h /
38 Port Name clean up dinesha 4522d 15h /
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4522d 17h /

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