URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

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Rev	Log message	Author	Age	Path
135	resynced with socgen, Release V1.0.0 changed tool lic to apache 2.0	jt_eaton	2774d 08h	/
134	Resynced database socgen now supports elaboration Bad news is that it is now alot slower.	jt_eaton	3284d 10h	/
133	Added Desing databases and foundation for elaborations tools	jt_eaton	3327d 11h	/
132	fixed permissions on tools/bin	jt_eaton	3359d 07h	/
131	Added elaboration databases and tools Added bus map creation tools	jt_eaton	3359d 08h	/
130	Dec 2014 major release trimmed out some IP replaced perl database with Berkeley	jt_eaton	3463d 01h	/
129	removed unneeded 6502 files	jt_eaton	3918d 07h	/
128	major cleanup added toolflows for sim,syn,documentation,linting and verilog added documentation tools	jt_eaton	3918d 07h	/
127	final cleanup before DAC	jt_eaton	4033d 03h	/
126	added mor1kx cleanup	jt_eaton	4086d 08h	/
125	Added two new 6502 cores in www.6502.org cleaned up sogen xml files and added module name control	jt_eaton	4131d 02h	/
124	beta release candidate 1 changed design.xml name aligned schema with filesystem	jt_eaton	4184d 05h	/
123	added support for ubuntu 12.10	jt_eaton	4198d 22h	/
122	Moved Nexys2 from opencores.org to digilentinc.com Moved jtag_rpc and or1k Busdefs into cde_jtag and or1200 components	jt_eaton	4207d 01h	/
121	cleaned up sims, added autogenerated test bench files removed mrisc and experimental or1k code	jt_eaton	4227d 07h	/
120	clean up componentGenerators names and directories sim + lint now synthesis TestBench	jt_eaton	4245d 07h	/
119	moved copyright files into /verilog changed cde copyright to apache from gplv3 split out tools into separate subdirectories changed design.xml files to socgen: namespace	jt_eaton	4280d 01h	/
118	optimized gen_verilog added padring support added configuration support added jtag sims added accellera candidate bus defs	jt_eaton	4315d 10h	/
117	added yellow pages tools	jt_eaton	4343d 05h	/
116	added build_header now use build_register for all spr components resynced or1200 code back to use orbuild toolchain	jt_eaton	4378d 02h	/
115	split or1200_cpu up into all ip-xact components removed dead files	jt_eaton	4422d 07h	/
114	moved or1200 connectivity out of verilog and into ip-xact added or1200_boot block removed force of 00 on lowest iwb_addr bits	jt_eaton	4434d 07h	/
113	started refactoring or1200	jt_eaton	4439d 23h	/
112	added more test sims removed unneeded files	jt_eaton	4449d 12h	/
111	split or1200 out into seperate test suite	jt_eaton	4451d 06h	/
110	split out more ip-xact components added sw sources	jt_eaton	4463d 04h	/
109	removed unused file	jt_eaton	4466d 03h	/
108	removed unneeded files	jt_eaton	4467d 10h	/
107	added designCfg files to all modules	jt_eaton	4467d 12h	/
106	checked in orp_soc project step 2	jt_eaton	4473d 05h	/

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