OpenCores
URL https://opencores.org/ocsvn/t51/t51/trunk

Subversion Repositories t51

[/] - Rev 51

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
51 New directory structure. root 5567d 23h /
50 initial version andreas 6267d 12h /
49 some improvements andreas 6430d 21h /
48 *** empty log message *** andreas 6599d 11h /
47 updated t8052 core andreas 6599d 18h /
46 some updates andreas 6599d 18h /
45 *** empty log message *** andreas 6599d 18h /
44 some updates and bugfixes andreas 6599d 18h /
43 bugfix for interrupts at stalled instructions andreas 6682d 12h /
42 *** empty log message *** andreas 6701d 10h /
41 some updates andreas 6701d 10h /
40 *** empty log message *** andreas 6701d 10h /
39 some updates for T8032 andreas 6701d 10h /
38 some updates andreas 6710d 18h /
37 some updates andreas 6710d 18h /
36 some updates andreas 6710d 21h /
35 some updates andreas 6710d 22h /
34 bugfix for mode 0 andreas 6719d 14h /
33 bugfix for JBC instruction andreas 6731d 19h /
32 bugfix for two subsequent movx instructions andreas 6768d 14h /
31 update andreas 6854d 13h /
30 Made some bugfixes andreas 6855d 16h /
29 Removed UNISIM library jesus 7865d 19h /
28 Added -n option and component declaration jesus 7893d 17h /
27 Added Leonardo .ucf generation jesus 7893d 17h /
26 Updated for ISE 5.1 jesus 7900d 13h /
25 Fixed typo jesus 7910d 05h /
24 Fixed for ISE 5.1 jesus 7910d 05h /
23 Xilinx SSRAM, initial release jesus 7920d 07h /
22 Removed write through jesus 7948d 04h /

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.