OpenCores
URL https://opencores.org/ocsvn/t51/t51/trunk

Subversion Repositories t51

[/] - Rev 52

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
52 Added old uploaded documents to new repository. root 5586d 20h /
51 New directory structure. root 5586d 20h /
50 initial version andreas 6286d 08h /
49 some improvements andreas 6449d 18h /
48 *** empty log message *** andreas 6618d 07h /
47 updated t8052 core andreas 6618d 14h /
46 some updates andreas 6618d 14h /
45 *** empty log message *** andreas 6618d 14h /
44 some updates and bugfixes andreas 6618d 14h /
43 bugfix for interrupts at stalled instructions andreas 6701d 08h /
42 *** empty log message *** andreas 6720d 06h /
41 some updates andreas 6720d 07h /
40 *** empty log message *** andreas 6720d 07h /
39 some updates for T8032 andreas 6720d 07h /
38 some updates andreas 6729d 14h /
37 some updates andreas 6729d 14h /
36 some updates andreas 6729d 17h /
35 some updates andreas 6729d 18h /
34 bugfix for mode 0 andreas 6738d 10h /
33 bugfix for JBC instruction andreas 6750d 15h /
32 bugfix for two subsequent movx instructions andreas 6787d 10h /
31 update andreas 6873d 09h /
30 Made some bugfixes andreas 6874d 12h /
29 Removed UNISIM library jesus 7884d 16h /
28 Added -n option and component declaration jesus 7912d 13h /
27 Added Leonardo .ucf generation jesus 7912d 13h /
26 Updated for ISE 5.1 jesus 7919d 09h /
25 Fixed typo jesus 7929d 01h /
24 Fixed for ISE 5.1 jesus 7929d 01h /
23 Xilinx SSRAM, initial release jesus 7939d 03h /

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.