OpenCores
URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] - Rev 79

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
79 ALU testbench added. gabrieloshiro 5594d 05h /
78 ZPG coded and simulated. creep 5594d 05h /
77 ZPG coded. Simulation is halfway. creep 5594d 06h /
76 ABS write instructions were not simulated.
Also added some initial ZPG simulation.
creep 5594d 06h /
75 First working version! gabrieloshiro 5594d 06h /
74 The file now describes who is doing what. creep 5594d 06h /
73 Added schedule file into the readme file. creep 5594d 06h /
72 Project management folder. creep 5594d 06h /
71 Four addressing modes are simulated: immediate, accumulator, implied and absolute.
The simulation was done using a testbench that contains a small memory inside.
creep 5594d 06h /
70 Fixed several timing. Registered outputs working.
Only three adressing modes coded, the previous coding was erased.
creep 5598d 03h /
69 Added signal origin/destination. creep 5598d 04h /
68 The FSM module is now parametrized.
Also, several changes were made to remove most of the lint warnings.
creep 5598d 05h /
67 File name change to lowercase. HAL says so! creep 5598d 07h /
66 File name change to lowercase. HAL says so! creep 5598d 07h /
65 Now the blocks are connected. gabrieloshiro 5599d 02h /
64 Constant were wrong. gabrieloshiro 5599d 02h /
63 Fixed several HAL warnings. Still plenty to do. creep 5599d 02h /
62 The DUT file name changed. creep 5599d 02h /
61 File name change to lowercase. HAL says so! creep 5599d 03h /
60 File name change. HAL says so! creep 5599d 03h /
59 I`ve fixed some latch creation. gabrieloshiro 5599d 03h /
58 ALU with all opcodes ready for simulation. gabrieloshiro 5599d 03h /
57 A very simple testbench that checks the execution for a single instruction, i.e. no memory. creep 5599d 04h /
56 Several changes in the output logic to respect the pipelining. creep 5599d 04h /
55 ALU has all opcodes now! Comments inside ALU are completely wrong. gabrieloshiro 5599d 05h /
54 Processor Status register modified. gabrieloshiro 5599d 07h /
53 Added default header. creep 5599d 11h /
52 Removed unecessary always block. creep 5600d 03h /
51 Some first ideas on testbench. creep 5600d 03h /
50 Testing. creep 5600d 05h /

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.