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Rev Log message Author Age Path
26 Fixed instruction timing for POP and DJNZ jesus 7954d 20h /
25 IX/IY timing and ADC/SBC fix jesus 7956d 06h /
24 no message jesus 7962d 03h /
23 Fixed T2Write jesus 7962d 03h /
22 Added 8080 top level jesus 7962d 03h /
21 no message jesus 7967d 02h /
20 Updated for new T80s generic jesus 7967d 02h /
19 Initial version jesus 7967d 02h /
18 Added T2Write generic jesus 7967d 09h /
17 Removed write through jesus 7969d 01h /
16 no message jesus 7969d 05h /
15 Added clock enable and fixed IM 2 jesus 7976d 04h /
14 Changed to Xilinx ROM jesus 7995d 16h /
13 Initial import jesus 7995d 16h /
12 Initial import jesus 7995d 17h /
11 Added support for XST jesus 7995d 17h /
10 Added dummy files jesus 7995d 18h /
9 Initial import jesus 7997d 04h /
8 Fixed refresh address and DJNZ instruction jesus 7997d 05h /
7 Initial import jesus 7997d 06h /
6 Fixed wide rom .ucf generation jesus 8074d 06h /
5 Now it seems to work jesus 8074d 06h /
4 Fixed xilinx ROM generation jesus 8075d 09h /
3 Initial commit, incomplete jesus 8077d 11h /
2 Initial import jesus 8092d 20h /
1 Standard project directories initialized by cvs2svn. 8092d 20h /

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