URL https://opencores.org/ocsvn/v586/v586/trunk

Subversion Repositories v586

[/] - Rev 101

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Rev	Log message	Author	Age	Path
101	add ddr interface mig7 xilinx xci ip	ultro	2906d 19h	/
100	add crossbar for nexys4 ddr with 128megabyte ram window	ultro	2906d 19h	/
99	remove phy_intn from xdc constraints as it is not used inside design wi th etherlite.	ultro	2948d 04h	/
98	update tbench and add mii to rmii converter ip from xilinx	ultro	2948d 14h	/
97	update periph and TOP	ultro	2948d 14h	/
96	update periph , uart is not inside	ultro	2948d 14h	/
95	update boot.mem accordingly to test.s cleanup	ultro	2950d 17h	/
94	clean up test.s	ultro	2950d 17h	/
93	added stub for keyboard	ultro	2951d 06h	/
92	added doc	ultro	2951d 07h	/
91	update netlists cosmetics	ultro	2951d 19h	/
90	updated cosmetic periph.v	ultro	2951d 21h	/
89	add 3x rtl files	ultro	2951d 22h	/
88	remove axi ip standalone	ultro	2951d 22h	/
87	update rtl for boot.mem	ultro	2951d 22h	/
86	update tbench	ultro	2951d 22h	/
85	supress 2 files acu.v and clk_wiz.vhd	ultro	2951d 22h	/
84	add Xilinx xci ip repo	ultro	2951d 23h	/
83	cleanup	ultro	2951d 23h	/
82	delete ucf	ultro	2951d 23h	/
81	update linux patch instead of config , to generated the kinux kernel	ultro	2951d 23h	/
80	update TOP_SYS.xdc for sd & gpios	ultro	2952d 00h	/
79	replaced linux with SD version and root.bon with initramfz.cpio.gz from buildroot 2016.02 with micropython and e2fs utilities	ultro	2952d 00h	/
78	fix mci	ultro	2952d 00h	/
77	update mcs files with axi version and buildroot 2016.02 and micropython	ultro	2952d 00h	/
76	remove useless file	ultro	2952d 00h	/
75	update for axi version	ultro	2952d 01h	/
74	update boot for one file 32bits instead of 4x files 8bit/bytewise	ultro	2952d 01h	/
73	Added the zip file for an AXI version of the IP for Vivado Xilinx tool You can unzip the file into a directory and add IP to your personal IP repository	ultro	3063d 13h	/
72	update ROM boot	ultro	3236d 16h	/

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Subversion Repositories v586

[/] - Rev 101

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