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Rev Log message Author Age Path
31 sync FIFO updated unneback 4917d 03h /
30 updated counter for level1 and level2 function unneback 4917d 04h /
29 updated counter for level1 and level2 function unneback 4917d 04h /
28 added sync simplex FIFO unneback 4918d 05h /
27 added sync simplex FIFO unneback 4918d 05h /
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 4918d 06h /
25 added sync FIFO unneback 4918d 20h /
24 added vl_dff_ce_set unneback 4920d 04h /
23 fixed port map error in async fifo 1r1w unneback 4920d 18h /
22 added binary counters unneback 4920d 23h /
21 reg -> wire in and or mux in logic unneback 4921d 20h /
20 naming convention vl_ unneback 4923d 06h /
19 naming convention vl_ unneback 4923d 06h /
18 naming convention vl_ unneback 4923d 07h /
17 unneback 4986d 20h /
16 converting utility for ROM unneback 4987d 07h /
15 added delay line unneback 4993d 04h /
14 reg -> wire for various signals unneback 4993d 09h /
13 cosmetic update unneback 4993d 10h /
12 added wishbone comliant modules unneback 4994d 06h /
11 async fifo simplex unneback 4994d 21h /
10 added dff_ce_clear unneback 4996d 20h /
9 added dff_ce_clear unneback 4996d 20h /
8 added dff_ce_clear unneback 4996d 20h /
7 mem update unneback 4996d 21h /
6 added library files unneback 5009d 22h /
5 memories added unneback 5009d 22h /
4 added counters unneback 5014d 02h /
3 various updates
counter added
unneback 5016d 21h /
2 initial check-in unneback 5017d 21h /

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