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Rev Log message Author Age Path
44 added target independet IO functionns unneback 4868d 22h /
43 added logic for parity generation and check unneback 4873d 01h /
42 updated mux_andor unneback 4877d 01h /
41 typo in registers.v unneback 4877d 02h /
40 new build environment with custom.v added as a result file unneback 4877d 03h /
39 added simple port prio based wb arbiter unneback 4878d 00h /
38 updated andor mux unneback 4878d 00h /
37 corrected polynom with length 20 unneback 4883d 20h /
36 added generic andor_mux unneback 4885d 05h /
35 added vl_mux2_andor and vl_mux3_andor localparam unneback 4885d 16h /
34 added vl_mux2_andor and vl_mux3_andor unneback 4885d 16h /
33 updated wb3wb3_bridge unneback 4898d 18h /
32 added vl_pll for ALTERA (cycloneIII) unneback 4906d 04h /
31 sync FIFO updated unneback 4925d 23h /
30 updated counter for level1 and level2 function unneback 4925d 23h /
29 updated counter for level1 and level2 function unneback 4926d 00h /
28 added sync simplex FIFO unneback 4927d 01h /
27 added sync simplex FIFO unneback 4927d 01h /
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 4927d 02h /
25 added sync FIFO unneback 4927d 16h /
24 added vl_dff_ce_set unneback 4928d 23h /
23 fixed port map error in async fifo 1r1w unneback 4929d 14h /
22 added binary counters unneback 4929d 19h /
21 reg -> wire in and or mux in logic unneback 4930d 15h /
20 naming convention vl_ unneback 4932d 02h /
19 naming convention vl_ unneback 4932d 02h /
18 naming convention vl_ unneback 4932d 02h /
17 unneback 4995d 16h /
16 converting utility for ROM unneback 4996d 03h /
15 added delay line unneback 5002d 00h /

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